Integration of security modules on an integrated circuit

DETAILED DESCRIPTION In accordance with the preferred embodiment of the present invention, an integrated circuit includes secure logic that requires protection.
Secure assurance logic protects the secure logic.
The secure assurance logic includes a plurality of protection modules that monitor the occurrence of insecure conditions.
Each protection module monitors a different type of insecure condition.
Each protection module asserts an alarm signal when an associated insecure condition is detected.
The alarm signals asserted by the plurality of protection modules are stored.
In the preferred embodiment, once an alarm signal is asserted, the alarm signal is received by a first register.
A second register is used for masking the alarm signals.
The masking performed by the second register is used to prevent selected alarm signals from being propagated.
This allows certain alarms to be blocked during testing of the secure assurance logic.
A third register stores the alarm signals that have been asserted but have not been masked by the second register.
The integrated circuit can be reset when an alarm signal is detected.
The plurality of protection monitors include, for example one or more of the following: a high frequency monitor that detects when a monitored clock exceeds a predetermined frequency, a low frequency monitor that detects when a monitored clock is less than a predetermined frequency, a single event detector monitor that monitors single event upsets within the integrated circuit, a reset monitor that monitors an amount of times the integrated circuit is reset, and a voltage detector that monitors for invalid voltage levels.
In addition, the secure assurance logic generally includes a power-on-reset circuit for resetting the integrated circuit to a known state upon power-up of the integrated circuit.
The above-described integration of the protection modules into secure assurance logic requires that someone attacking the security features of the integrated circuit must simultaneously defeat more than one security component