 Redundancy analyzer for automatic memory tester |
| What is claimed is: 1. Memory test apparatus for testing a memory under test (MUT) formed from ... |
|
| Method and apparatus for testing memory devices and displaying results of such tests |
| The present invention provides an apparatus and method for testing a semiconductor device, and in ... |
|
| Feedback shift register |
| OF THE PREFERRED EMBODIMENT FIG. 6 illustrates a preferred embodiment of the feedback shift ... |
|
| Laser apparatus |
| Therefore, the primary object of the present invention is to provide a laser apparatus wherein a ... |
|
| Multiple I/O bus virtual broadcast of programmed I/O instructions |
| According to the present invention, these and other objects and advantages are achieved in a method ... |
|
| Personal computer memory bank parity error indicator |
| Referring now to the drawing, a personal computer includes a microprocessor 10 connected to a main ... |
|
| Circuit for selectively preventing a microprocessor from posting write cycles |
| OF THE PREFERRED EMBODIMENT Referring now to FIG. 1, an exemplary computer system S incorporating ... |
|
| Method and system for concurrent computer transaction processing |
| The present invention is directed to a method, system, and bus agent for concurrent transaction ... |
|
| Real-time synchronization of concurrent views among a plurality of existing applications |
| A synchronization system includes a motion event synchronizer and multiple application ... |
|
|
Jtag testing of buses using plug-in cards with Jtag logic mounted thereon
| Details |
Inventors: Mote, Jr., L. Randall;
Assignee: Samsung Electronics Co., Ltd. (Seoul, KR)
Primary Examiner: Beausoliel, Jr.; Robert W.
Assistant Examiner: Iqbal; Nadeem
Attorney, Agent or Firm: Knobbe, Martens, Olson & Bear, LLP
A plug-in JTAG test card includes JTAG boundary scan circuitry which may be used to drive JTAG test data out onto portions of buses connected to peripheral plug-in slots. One or more of the JTAG plug-in test cards can be used to verify the integrity of each of the point-to-point connections on the buses which terminate in the peripheral plug-in slots. In one advantageous embodiment, the plug-in JTAG test cards simulate a dual in-line memory module (DIMM) or single in-line memory module (SIMM) cards which include scan test buffer circuitry but do not actually include memory chips so that an inexpensive plug-in card can be used to provide JTAG testing at the manufacturing level for multiple motherboards. In a particularly preferred embodiment, JTAG boundary scan buffer circuits, such as, for example, SN74ABT8245's, are used as test circuits rather than for their intended use as interface circuits. |
|
DETAILED DESCRIPTION A system for testing point-to-point connections on a circuit board using JTAG comprises the circuit board, including circuitry which is to be tested using JTAG.
A bus on the circuit board includes connection pins, while a plurality of plug-in peripheral or expansion slots are electrically coupled with the bus pins.
A plug-in JTAG test card further engages with one of the plug-in slots to establish an electrical connection thereto.
The test card includes JTAG test circuitry for driving test signals onto the bus pins via the plug-in slot engaged with the test card.
Finally, the system includes a JTAG test circuit in communication with the bus on the circuit board.
The test signals output by the test card are received by the JTAG test circuit for testing the integrity of point-to-point connections on the circuit board.
In a preferred embodiment, the JTAG test circuit comprises a second JTAG test card engaged with a second plug-in slot.
In an alternate preferred embodiment, the JTAG test circuit comprises an integrated circuit chip having JTAG test capability on the circuit board.
Under another aspect, the invention is a method of testing bus connections on a motherboard which interface with a plug-in slot.
The method comprises the step of providing a plug-in test card having JTAG test components, including a boundary scan register.
The test card is configured to plug into the plug-in slot.
The method further includes the steps of plugging the test card into the plug-in slot; shifting a test vector comprising data bits into the boundary scan register; outputting the test vector data bits from the boundary scan register over the bus connections via the plug-in slot; receiving the output test vector data bits via the bus connections; capturing the test vector data bits via the JTAG boundary scan register; shifting the test data out of the boundary scan register and into the JTAG tester; and comparing the received output test vector data bits to a predetermined output pattern in order to identify malfunctions in the bus connections
|
|
Fault Detection 
