Latch-up control for a CMOS memory with a pumped well

DETAILED DESCRIPTION An object of the present invention is to provide an improved power-up circuit for a DRAM.
Another object of the invention is to provide an improved latch-up protection circuit for a CMOS memory.
Yet another object of the invention is to improve latch-up protection during power-up of a DRAM.
These and other objects are achieved in a CMOS DRAM having an array of memory cells located at intersections of word lines and bit lines including transfer device transistors of a first conductivity type formed in an array well of a second conductivity type, and characterized as having a power-up condition for a time period following application of power to a first power supply terminal.
The memory has a pumping circuit, a word line driver, and a ramp control circuit.
The pumping circuit pumps the array well to a predetermined voltage There is thus an array well rise time during the power-up condition.
The word line driver raises the word lines to a predetermined voltage in response to entering the power-up condition.
The voltage on the word lines driven by the driver means is characterized as having a word line rise time.
The rise in word line voltage during the power-up condition is characterized as being capacitively coupled to the bit lines so that the bit lines rise in voltage at a bit line rise time.
The ramp control circuit causes the word line rise time during the power-up condition to be at least a predetermined minimum which will result in the bit line rise time being greater than the array well rise time.