Limited probes device testing for high pin count digital devices

DETAILED DESCRIPTION In accordance with a preferred embodiment of the present invention an integrated circuit is tested when input and output pads of the integrated circuit are unconnected to any external device.
In order to do this, for each of a subset of the unconnected input and output pads, a boundary scan register is provided.
A test vector is scanned serially into the boundary scan registers.
The test vector may then be applied to internal logic of the integrated circuit.
While the test is in progress, the value contained within each boundary scan register is also applied to an associated input pad so that the input pads of the device do not float.
In the preferred embodiment, when a response value of the internal logic of the integrated circuit is captured into each boundary scan register associated with an output pad, the value contained within each input pad boundary scan register continues to be applied to the internal logic through the associated input pad.
The response value can then be serially scanned out of the boundary scan registers for observation.
In order to implement the above-described testing methodology, boundary scan registers are designed with additional functionality.
For example, boundary scan registers that are to be connected to input pad type signals are designed to include a gate which connects the output of the boundary scan register and the associated pad during wafer testing.
Additionally, a selection means such as a multiplexor, is used to allow the output of the internal logic of the device to serve as input to the boundary scan register.
This increases the testability of the boundary scan circuit.
The present invention allows limited probes device testing for high pad count digital devices while the pads of the device remain unconnected to an external ATE.
This greatly increases the ability and economy of testing devices during wafer sorting.