Mechanism for enabling compliance with the IEEE standard 1149.1 for boundary-scan designs and tests

DETAILED DESCRIPTION The present invention provides a mechanism for boundary-scan design and test methodologies applicable to timing-critical high (above 200 MHz) speed clock designs, which complies with the IEEE standard 1149.
1.
In a first preferred embodiment, the mechanism includes a compliance-enabling apparatus (an enabler) for providing clocking and other signals necessary to embedded cells which use an internal scan cell architecture and which are non-compliant with the boundary scan standard.
The non-compliant cells are "embedded" in their functional logic designs rather than being disposed adjacent the I/O pins as is conventional with IEEE standard boundary-scan techniques.
In a second preferred embodiment, a second enabler works with a Test Access Port emulator to support devices that, due to their size limitations for example, do not include an IEEE standard 1149.
1 TAP controller.
The provided TAP emulator is about one-tenth the size of, and replaces, the IEEE standard TAP controller.
The mechanism thus allows a Device Under Test to function as an IEEE standard 1149.
1 compliant part.
Consequently, existing test tools for the IEEE boundary-scan standard can be fully utilized with devices incorporating the invention.
The invention permits a DUT to vary as follows: 1) the DUT does not have to have an internal TAP controller; 2) the DUT may have a TAP controller and both regular boundary-scan cells and embedded boundary-scan cells; or 3) the device may have only embedded boundary-scan cells with or without a TAP controller.
Level Sensitive Scan Design (LSSD) based scan cells can also use the invention.
Benefits gained from the invention include: 1) minimizing propagation delay due to boundary-scan cell functions; 2) reducing gate overhead in standard boundary-scan tests; 3) facilitating support for boundary-scan functions where an embedded coreware circuit's internal scan cells interface directly with the device package I/O pins; 4) enabling ATE tools to fully support tests and test vectors for scan cells that are non-compliant and utilize the embedded boundary-scan structure; 5) reducing overhead in board designs; 6) the enabler preferably being portable to fully-compliant boundary-scan ATE tools; 7) improving IC testability; 8) improving ASIC performance; 9) meeting all ASIC manufacturing test requirements; 10) reducing In-Circuit Test (ICT) development time; and 11) improving tester correlation and program reliability