Memory defect masking device

DETAILED DESCRIPTION Therefore, the main objective of the present invention is to provide a memory defect masking device to be used in combination with a plurality of memory devices which is capable of replacing the defective memory spaces of the memory devices, thereby permitting the memory devices to operate as if no defective memory space exists.
The memory defect masking device of the present invention can be adapted for use with different kinds of memory devices, such as DRAM units, SRAM units, PROM units, ROM units, Flash memory units and EEPROM units.
Accordingly, the preferred embodiment of a memory defect masking device of the present invention is to be used in combination with a plurality of memory devices which have a plurality of address lines, a plurality of data lines and a control input means for controlling read and write operations of the memory devices.
The memory defect masking device comprises at least one entry cell means including: an address cell means having a first memory means for storing the address of a defective memory space of the memory devices and an address comparator means for comparing a memory address present at the address lines with the address stored in the first memory means, said address comparator means generating a control signal to the control input means of the memory devices when the memory address present at the address lines tallies with the address stored in the first memory means, said memory devices being disabled upon reception of the control signal; and a data cell means connected to the data lines of the memory devices and controlled by the address cell means so as to act as a replacement for the defective memory space of the memory devices.