 Parasitic element extraction apparatus |
| It is an object of the present invention to solve at least the problems in the conventional ... |
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| Bist architecture for measurement of integrated circuit delays |
| The IC to be tested is provided with, in one embodiment, a two-wire test bus, which passes near ... |
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| Oscillator for measuring on-chip delays |
| FIG. 2 is a schematic diagram of an oscillator 200 configured, in accordance with the invention, ... |
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| Method and system for measuring signal propagation delays using ring oscillators |
| FIG. 2 is a schematic diagram of a conventional tester 200 connected to an FPGA 210 that has been ... |
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| Monitor TEG test circuit |
| OF THE PREFERRED EMBODIMENTS Referring now to the drawings, wherein like reference numerals ... |
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| IC substrate noise modeling including extracted capacitance for improved accuracy |
| An invention is described herein which provides methods and apparatus for modeling noise present in ... |
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| Method for performing coupling analysis |
| Deterministic evaluation of coupling noise voltage is a function of many physical and electrical ... |
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| Cell-based noise characterization and evaluation |
| OF THE INVENTION Aspects of the present invention include methods and apparatus for designing an ... |
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Memory output circuit
| Details |
Inventors: Monk, Trevor K.;
Assignee: Standard Telephones & Cables (London, GB2)
Primary Examiner:
Assistant Examiner:
Attorney, Agent or Firm:
An energy efficient output circuit for a static random access memory includes a pair of output transistors each driven by a bootstrapped driver stage. This requires less current than conventional amplifier chain. |
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DETAILED DESCRIPTION I claim: 1.
In a semiconductor memory, an output circuit comprising: an output transistor series pair, each transistor of said pair being coupled to a respective bootstrapped driver circuit; driver means for driving said bootstrapped driver circuits with signals of a voltage level less than the operating voltage of the memory and corresponding to memory output data; and said driver means including a first preamplifier serving as a sense amplifier, a second preamplifier connected to the output of said first preamplifier and provided with positive capacitive feedback, and a logic level converter having an output pair of source follower transistors provided with cross-coupled load transistors, the sources of the load transistors being connected to circuit ground.
2.
A circuit in accordance with claim 1, wherein each of said load transistors comprises a plurality of parallel-connected transistors having different threshold voltages.
3.
A circuit in accordance with claim 1, wherein said first preamplifier, said second preamplifier and said logic level converter comprise balanced stages.
4.
In a semiconductor memory, an output circuit fabricated by an NMOS process and comprising: an output transistor series pair, each transistor of said pair being coupled to a respective bootstrapped driver circuit; driver means for driving said bootstrapped drive circuits with signals of a voltage level less than the operating voltage of the memory and corresponding to memory output data; and said driver means including a first preamplifier serving as a sense amplifier, a second preamplifier connected to the output of said first preamplifier and provided with positive capacitive feedback, and a logic level connecter having an output pair of source follow transistors provided with cross-coupled load transistors, the sources of the load transistors being connected to circuit ground.
Description:
This invention relates to semiconductor memories and in particular to output circuits for such memories
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Fault Detection 
