Memory with page mode

DETAILED DESCRIPTION We claim: 1.
In a memory comprising first and second arrays, each array comprising a plurality f memory cells arranged into rows and columns, each of said rows having a respective binary address, a method of accessing a plurality of rows having sequential binary address in response to receipt by the memory of a single binary address signal, comprising the steps of: a) accessing a first row of memory cells in said first array; b) accessing a first row of memory cells in said second array, while restoring said first row of memory cells in said first array; c) accessing a second row of memory cells in said first array, while restoring said second row of memory cells in said first array; (d) accessing a second row of memory cells in said second array, while restoring said second row of memory cells in said first array; and e) restoring said second row of memory cells in said second array.
2.
A memory comprising first and second arrays, each array comprising a plurality of memory cells arranged into rows that are accessed in response to a binary address signal, each of said rows being assigned binary addresses, wherein first and second rows having adjacent binary addresses are located n said first and second arrays, respectively, and means for accessing said first and second arrays sequentially by accessing rows having adjacent binary addresses by sequentially incrementing or decrementing a received binary address signal.
3.
A memory having a plurality of rows and columns and operable in a given page mode cycle such that a row address is selected for a row cycle and within said row cycle a plurality of column cycles are performed to access the memory at selected column addresses, wherein said memory additionally comprises control means for stepping the row address for selected column cycles within said given page mode cycle.
4.
A memory as claimed in claim 3 wherein said control means is responsive to a row change signal supplied to said memory when a column address strobe becomes active for stepping said row address