Method and apparatus for allocating display memory and main memory employing access request arbitration and buffer control

DETAILED DESCRIPTION The present invention, generally speaking, provides a low-cost, moderate performance small computer system by allowing a single sharable block of memory to be independently accessible as graphics or main store memory.
Allocation of the memory is selected programmably, eliminating the need to have the maximum memory size for each block simultaneously.
Performance penalties are minimized by dynamically allocating the memory bandwidth on demand rather than through fixed time slices.
A reallocatable memory subsystem enables transparent transfer of memory function of a lower-performance memory such as DRAM to occur in conjunction with a memory upgrade to a higher-performance memory such as VRAM, for example.
More particularly, an apparatus for use in a computing machine including a CPU and a first memory includes memory slots, configuration circuitry for enabling allocation of a second memory as display memory and the first memory as main memory responsive to a second memory having a different performance level than the first memory being added to the memory slots; and means for allowing substantially independent access to the first memory and the second memory.
Circuitry for allowing substantially independent access may include a memory controller including arbitration circuitry for arbitrating among a plurality of requests for access to the first and second memories, a first data path connected to the arbitration circuitry and including a first buffer store for facilitating exchange of data with the first memory, a second data path connected to the arbitration circuitry and including a second buffer store for facilitating exchange of data with the second memory, and control circuitry connected to the configuration circuitry and responsive to one or more signals applied to the apparatus, the signals including address, data and control signals, for causing at least some of the data signals to be applied to only one of the first and second data paths.