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Replacement data error detector
A cache is described which includes an error circuit for detecting errors in the replacement data. If an error is detected, the cache may update the replacement data to ...
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Soft error detection in high speed microprocessors
The present invention provides aspects for soft error detection for a superscalar microprocessor. The aspects include a first pipeline, the first pipeline including a ...
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Semiconductor integrated circuit device, manufacturing method thereof, and driving method for the same
To solve the above-described problems, the present invention employs the below-mentioned means. As a first means, means for storing therein trimming data, means for ...
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Integration of security modules on an integrated circuit
In accordance with the preferred embodiment of the present invention, an integrated circuit includes secure logic that requires protection. Secure assurance logic ...
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Method and system for storing device test information on a semiconductor device using on-device logic for determination of test results
OF THE INVENTION A schematic diagram of an embodiment of the present invention is shown in FIG. 1. An integrated circuit device is indicated at 1, and the integrated ...
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Semiconductor memory with a multiplexer for selecting an output for a redundant memory access
The invention may be incorporated into an integrated circuit memory with redundant memory cells, by way of a circuit that controls the coupling of a redundant sense ...
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Method and apparatus for inhibiting a predecoder when selecting a redundant row line
One aspect of the invention comprises a circuit for replacing a defective signal path of a plurality of like signal paths with a redundant signal path. The circuit ...
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Random access memory having a flexible array redundancy scheme
The present invention is a wide I/O Random Access Memory (RAM) and the architecture and redundancy scheme, therefor. If the RAM is large, it is divided into units. For ...
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Integrated circuit chip with a wide I/O memory array and redundant data lines
The present invention is an integrated circuit chip with a RAM or a RAM macro with at least one spare array element and the decode and redundancy scheme therefor. The ...
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Improved logic cell array using CMOS E.sup.2 PROM cells
OF ILLUSTRATIVE EMBODIMENT Referring now to the drawings, FIG. 1 is a schematic block diagram of a logic cell array. As described by Landry, supra, one commercially-...
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