Method and apparatus for correcting data errors

DETAILED DESCRIPTION Broadly speaking, the present invention relates to an error correcting method and apparatus which shortens the time needed to perform error correction using a buffer memory.
The present invention can be implemented in numerous ways including as an apparatus and a method.
The present invention provides a method of correcting an error of block data having a matrix form including a plurality of rows of data and a plurality of columns of data.
The method includes performing a row error correction by using the plurality of rows of data to produce row-corrected block data, and performing column error correction by using the plurality of columns of data to produce column-corrected block data.
At least one of the performing row error correction and the performing column error correction operates using a plurality of rows or columns of data in units of a predetermined number of rows or columns to provide error correction for the plurality of rows or columns in parallel.
The present invention also provides a method of mapping block data into a memory.
The block data is in a matrix form and has a plurality of rows of data and a plurality of columns of data.
The method includes providing a memory having a data bus and a plurality of limited memory areas, the memory being designed so that when a part of block data is stored in one limited memory area, a speed of accessing the one limited memory area is faster than an access speed from one limited memory area to another limited memory area, setting a width of the data bus of the memory wide enough to permit passing of a plurality of columns of data in units of a predetermined number of columns, storing the block data in individual limited memory areas of the memory via the data bus, in unit of a row, so that a part of a plurality of rows of data is stored in one limited memory area, and subsequently reading columns of data, associated with the part of the plurality of rows of data stored in the individual limited memory areas, from the memory via the data bus in units of the predetermined number of columns