Method and apparatus for correcting misaligned instruction data

DETAILED DESCRIPTION One aspect of the invention relates to a method useful in a microprocessor having a plurality of execution units, rename registers, architectural registers and a cache for storing blocks of data, each cache block having a plurality of words, for aligning data bytes stored in separate words.
In one embodiment, the method comprises the steps of reading a first word from the cache; rotating the first word to align at least one byte of the first word with a first byte of a rename register; storing the at least one byte of the first word in the rename register; reading a second word from the cache; rotating the second word to align at least one byte of the second word with a second byte of the rename register; and storing the at least one byte of the second word in the rename register.
Another aspect of the invention relates to a circuit for aligning bytes stored in separate words of a microprocessor cache.
In one embodiment, the circuit comprises means for reading a first word from the cache; means for rotating the first word to align at least one byte of the first word with a first byte of a rename register; means for storing the at least one byte of the first word in the rename register; means for reading a second word from cache; means for rotating the second word to align at least one byte of the second word with a second byte of the rename register; and means for storing the at least one byte of the second word in the rename register.