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 Method and apparatus for enhancing data rate in processing ECC product-coded data arrays in DVD storage subsystems and the like

Details
Inventors: Michigami, Toru; Tanaka, Keisuke;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Tu; Christine T.
Assistant Examiner:
Attorney, Agent or Firm: R. Bruce Brodie

A method and apparatus for high-speed memory management of ECC product-coded data arrays read back from DVD storage subsystems in which rows of length Y.ltoreq.2.sup.N.times.(2m+1) of the array are read from disk and written in alternate blocks of 2.sup.N bytes per block and (2m+1) blocks per row into successive addresses of a synchronous dynamic random access memory (SDRAM) operable both as a buffer and an interleaved pair of memories. Array data is subjected to detection and correction of error and/or erasure by ECC processing of data extracted from and rewritten into the SDRAM, the array being extracted, ECC processed, and rewritten to and from the SDRAM in block interleave column major order and then in block interleave row major order.

DETAILED DESCRIPTION What is claimed is: 1.
A machine-implementable method for enhancing the data transfer rate in an arrangement formed by an ECC processor coupling a first memory, said arrangement detecting and correcting errors and erasures responsive to a source of error correction-coded (ECC) product data arrays, each product-coded array having a first predetermined number of rows of Y bytes per row and a second predetermined number of columns, said arrangement writing each data array into a first memory, transferring data from the array in the first memory to the ECC processor, transferring corrected data from the ECC processor, and writing said transferred corrected data back into the first memory, comprising the steps of: (a) transferring each row of the data array from the source in row major order in blocks of 2.
sup.
N bytes per block and (2 m+1) blocks per row, and writing consecutive blocks (1.
sup.
st row--A.
sub.
0, B.
sub.
0, A.
sub.
1 ; 2.
sup.
nd row--B.
sub.
1, A.
sub.
2, B.
sub.
2, .
.
.
) into successive alternate addresses (A.
sub.
0, A.
sub.
1, A.
sub.
2 ; B.
sub.
0, B.
sub.
1, B.
sub.
2) in a pair of independently accessible linear address spaces in the first memory operated in an interleaved manner, N and m being positive integers satisfying the constraint Y.
ltoreq.
2.
sup.
N.
times.
(2 m+1); and (b) extracting data, ECC correcting the extracted data, and rewriting corrected data to and from successive addresses in the linear address spaces in the first memory in block interleave array row major order and then in block interleave array column major order.
2.
The method according to claim 1, wherein each data array has a row direction and a column direction, and further wherein each product data array is encoded in a first linear systematic ECC as one selected from a set consisting of a block ECC and a cyclic ECC, said first ECC being defined over the array in the row direction, and still further wherein each product data array is encoded in a second linear systematic ECC as one selected from a set consisting of a block ECC and a cyclic ECC, said second ECC being defined over the array in the column direction



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