DETAILED DESCRIPTION OF THE INVENTION A method and software for failure detection of logic nodes within an integrated device utilizing functional test vectors and scan mode are described.
In the following description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the present invention.
However, it will be apparent to one skilled in the art that these specific details are not required in order to practice the present invention.
FIG.
1 illustrates a diagram of a logic block 100 utilized by an embodiment of the present invention.
The logic block 100 represents internal logic and a scan path within an integrated device.
Also, the logic block 100 supports two modes of operation, a functional operation mode to perform various commands and requests, and a scan test mode for debug analysis.
The logic block receives inputs, I1 and I2, labeled as 114 and 116, and logic clouds 102, 104, 106, 108 and 110 generate an output, O1.
A plurality of flip-flops 126, 128, 130, and 132 store the logic values in response to a clock signal 134.
A plurality of multiplexers 118, 120, 121, 122 and 124 select an input to forward to the plurality of flip-flops.
A scan enable signal 112 is the control signal for the multiplexers.
The logic cloud 102 receives the inputs, I1 and I2, and comprises a plurality of logic gates including AND, OR, NOR, etc.
An output node, N1, from the logic cloud 102 and the input I1 are the two inputs to the multiplexer 118.
In one embodiment, the I1 input is the scan input for receiving an external scan vector.
For the scan test mode, the multiplexer 118 selects the I1 input if the scan enable signal is a logic high.
Otherwise, the multiplexer selects the output node N1 during the functional operation mode.
The flip-flop 126 receives an input at the data port, D, from the multiplexer 118 on the rising edge of the clock signal 134.
An output, Q, of the flip-flop 126 is coupled to the logic cloud 104 and multiplexer 120.
The remaining logic clouds 104-110, output nodes N2-N4, and flip-flops 128-132 operation in a similar manner as previously described for the multiplexer 118, flip-flop 126, and logic cloud 102
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Fault Detection 
