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Home Fault Detection Method-and-apparatus-for-inhibiting-a-predecoder-when-selecting-a-redundant-row-line

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 Method and apparatus for inhibiting a predecoder when selecting a redundant row line

Details
Inventors: Kersh, III, David V.; Norwood, Roger D.;
Assignee: Texas Instruments Incorporated (Dallas, TX)
Primary Examiner: Clawson, Jr.; Joseph E.
Assistant Examiner:
Attorney, Agent or Firm: Nerrings; Ronald O., Kesterson; James C., Donaldson; Richard L.

A circuit is provided for replacing a defective signal path (94) of a plurality of like signal paths with a redundant signal path (95, 96). A redundant decoder (72) is programmable to respond to a plurality of predetermined addressing signals (RFn) that normally operate to address the defective signal path (94, ROWL1R and ROWL1L). The redundant decoder is operable to generate a disable signal (RREN) in response to the predetermined addressing signals (RFn) and also is operable to select a redundant signal path (95, 96) in response thereto. A decoding circuit (70, 74) normally decodes selected ones of a plurality of addressing signals (RFn) and selects at least one of a plurality of signal paths in response thereto. The decoding circuit (70, 74) is coupled to the redundant decoder (72) for receiving the disable signal (RREN) therefrom. In response to receiving this disable signal (RREN) the decoding circuit (70, 74) will not decode the preselected addressing signals (RFn).

DETAILED DESCRIPTION One aspect of the invention comprises a circuit for replacing a defective signal path of a plurality of like signal paths with a redundant signal path.
The circuit comprises a redundant decoder programmable for responding to a plurality of predetermined addressing signals corresponding to the defective signal path.
The decoder is operable to generate a disable signal and to select a redundant signal path in response to the predetermined addressing signals.
A decoding circuit for decoding selected ones of a plurality of addressing signals and selecting at least one of a plurality of signal paths in response thereto is provided, and is coupled to the redundant decoder for receiving the disable signal.
The decoding circuit will fail to decode the predetermined addressing signals in response to receiving the disable signal.
In another aspect of the invention, the decoding circuit includes a predecoder and a bank of decoders.
The bank of decoders are coupled to the predecoder with a plurality of predecoder lines.
The predecoder is coupled to the redundant decoder by the disable signal, and becomes disabled by being blocked from selecting one of the predecoder lines in connecting a global signal source to the decoders.
In a further aspect of the invention, the redundant decoder comprises a plurality of addressing transistors.
Each of the transistors is operable by receipt of a respective addressing signal to couple a node to a supply of a first voltage.
Each addressing transistor is coupled to the node through an isolation device.
The redundant decoder is programmed by causing selected ones of the isolation devices to isolate respective transistors from the node.
Then, when a set of addressing signals is received by the redundancy decoder which corresponds to the defective signal path, the addressing transistors will be unable to couple the node to the supply of the first voltage.
The node therefore remains at a second voltage, which causes circuitry coupled to it to both generate the disable signal and to connect a redundant row line to the global signal source



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