Method and apparatus for power management of an integrated circuit

DETAILED DESCRIPTION Embodiments of the present invention include a clock distribution system and clock interrupt system for an integrated circuit device.
Ignoring effects associated with the matched stages, the present invention includes a clock distribution and interrupt system for providing clock signals with less than 100 picoseconds of skew to various components of an integrated circuit device.
Considering the effects of the matched input stages, the above value may approach 300 picoseconds due to processing imperfections and imperfections associated with the matching input stages.
The present invention utilizes several stages of drivers to evenly supply the distributed clock signals and each stage has RC matched input lines.
The present invention advantageously locates the matched stages and clock drivers within the power supply ting of the integrated circuit located on the periphery of the microprocessor topology.
This is done in order to better predict the topology surrounding these lines to match the capacitance of these lines.
Further, this metal level offers a larger width dimension line (since as a top layer it may be thicker) having less resistance per unit area and also generally avoids spatial competition with other IC components and circuitry.
The present invention additionally offers the capability of selectively powering down various components within the integrated device with a power management unit and enable network that is included within the clock distribution system.
Specifically, an embodiment of the present invention is described in an integrated circuit having a plurality of circuit components and a clock generator circuit, an apparatus for supplying a plurality of synchronous clock signals to the plurality of circuit components, the plurality of synchronous clock signals referenced from the clock generator circuit, the apparatus including: a plurality of global clock driver means uniformly disposed along a periphery of the integrated circuit, the plurality of global clock driver means for generating a plurality of synchronous clock signals; and a plurality of feeder means, each feeder means coupled to a global clock driver means, the plurality of feeder means for supplying the plurality of synchronous clock signals from the periphery of the integrated circuit to the plurality of circuit components of the integrated circuit