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Method and apparatus for testing memory devices and displaying results of such tests
| Details |
Inventors: Lindsay, Brent;
Assignee: Micron Technology, Inc. (Boise, ID)
Primary Examiner: Beausoliel, Jr.; Robert W.
Assistant Examiner: Elisca; Pierre E.
Attorney, Agent or Firm: Dorsey & Whitney LLP
An apparatus and method for testing a semiconductor device allows error data to be displayed, in real time, based on the physical locations of the errors on the semiconductor device. A mapping circuit includes a router circuit, an error catch memory, and a topological circuit. The router circuit converts logical addresses employed by the semiconductor device to physical addresses employed by the error catch memory so that error data is appropriately routed from locations in the semiconductor device to corresponding locations in the error catch memory. The topological circuit then converts the physical addresses of the error data in the error catch memory to spatial addresses for allowing a host computer to rapidly display such errors as a bit map display on a visual display device. The router and topological circuits are preferably field programmable gate arrays or programmable read only memories so that the host computer can reprogram them for different semiconductor devices to be tested. |
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DETAILED DESCRIPTION The present invention provides an apparatus and method for testing a semiconductor device, and in real-time, displaying the spatial locations of errors on a display device, where the locations of the errors on the display device correspond to physical locations on a die containing the semiconductor device.
The present invention preferably employs a field programmable gate array ("FPGA") or hardware implemented look-up table for rapidly routing the error data received from an error compare circuit to an error catch memory in a manner such that the error data is stored in the error catch memory at physical addresses that correspond to logical addresses employed by the device being tested.
As a result, the router circuit continually routes error data to particular physical locations in the error catch memory.
A topological circuit, such as an FPGA, remaps the physical locations of the error data from the error catch memory to spatial locations for display on a bitmapped display device such as a CRT.
Therefore, the topological circuit can also continually route the error data from the error catch memory, through the host computer, for display on the display device.
Overall, the router circuitry continually routes the logical addresses of error data to appropriate physical addresses in the error catch memory for the device being tested, while the topological circuitry continually maps the physical addresses of the error data to spatial addresses for display on the bitmap display device, all while the host computer is performing other functions such as applying a test pattern to the device, controlling the display device, etc.
By being implemented in hardware, the router and topological circuits are considerably faster than the prior art approach of performing routines by the host computer.
Additionally, the router and topological circuits can operate in parallel with the host computer, thereby improving the overall speed of the testing apparatus of the present invention.
As a result, while the Teradyne system requires a mainframe or supercomputer for fast testing of complex semiconductor devices, the present invention can employ a minicomputer or personal computer as its host computer, thereby realizing a much more cost-effective testing apparatus
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Fault Detection 
