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Optimizing repeaters positioning along interconnects
A preferred embodiment of the present invention provides an aspect of interconnect design for optimizing delay characteristics of interconnects. The preferred embodiment ...
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Method and apparatus for placing repeaters in a network of an integrated circuit
OF THE PREFERRED EMBODIMENT(S) FIG. 1 is a schematic diagram of a network or net 100 that is used to illustrate repeater insertion in accordance with the present ...
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Parasitic element extraction apparatus
It is an object of the present invention to solve at least the problems in the conventional technology. The parasitic element extraction apparatus extracts parasitic ...
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Voltage controlled oscillator including voltage controlled delay circuit with power supply noise isolation
Accordingly, one object of the present invention is a VCO which is less sensitive than prior art VCOs to power supply noise. Another object of the present invention is a ...
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Bist architecture for measurement of integrated circuit delays
The IC to be tested is provided with, in one embodiment, a two-wire test bus, which passes near each circuit node of interest. Each node which is an input to a delay ...
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Oscillator for measuring on-chip delays
FIG. 2 is a schematic diagram of an oscillator 200 configured, in accordance with the invention, to include a pair of similar test circuits 210A and 210B. Test circuits ...
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Method and system for measuring signal propagation delays using ring oscillators
FIG. 2 is a schematic diagram of a conventional tester 200 connected to an FPGA 210 that has been configured to implement an oscillator and to determine the period and ...
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Monitor TEG test circuit
OF THE PREFERRED EMBODIMENTS Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views, and ...
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System, IC chip, on-chip test structure, and corresponding method for modeling one or more target interconnect capacitances
In summary, the present invention comprises a system, an IC chip, a test structure formed on the IC chip, and a corresponding method for modeling one or more target ...
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IC substrate noise modeling including extracted capacitance for improved accuracy
An invention is described herein which provides methods and apparatus for modeling noise present in an integrated circuit substrate. This is accomplished by obtaining a ...
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