|
|
Semiconductor integrated circuit boundary scan test with multiplexed node selection
The object of the present invention is therefore to provide a semiconductor integrated circuit having a test circuit built therein to facilitate the board test of ...
|
|
|
Testing the integrity of an electrical connection to a device using an onboard controllable signal source
OF THE INVENTION The present invention is directed to systems and a method for testing the integrity of an electrical connection mounted on a circuit assembly using an ...
|
|
|
Apparatus for I/O leakage self-test in an integrated circuit
According to one embodiment, an integrated circuit is disclosed that includes a first input/output (I/O) circuit and a leakage detection circuit coupled to the first I/O ...
|
|
|
Mechanism for enabling compliance with the IEEE standard 1149.1 for boundary-scan designs and tests
The present invention provides a mechanism for boundary-scan design and test methodologies applicable to timing-critical high (above 200 MHz) speed clock designs, which ...
|
|
|
Independent remote computer maintenance device
It is an object of the present invention to provide an independent computing device for diagnosing and repairing a host computer. It is another object of the present ...
|
|
|
Method, system, and program for diagnosing a computer in a network system
OF THE PREFERRED EMBODIMENTS In the following description, reference is made to the accompanying drawings which form a part hereof and which illustrate several ...
|
|
|
System and method for identifying executable diagnostic routines using machine information and diagnostic information in a computer system
FIG. 1 is a diagram illustrating an embodiment of a computer system. FIG. 1 depicts a computer system 100. Computer system 100 includes a processor 110, a chipset 120, ...
|
|
|
Methods for quantitative analysis by tandem mass spectrometry
Embodiments of the present invention provide methods for deconvoluting contributions of a plurality of analytes utilizing a tandem mass spectrometry, or MS.sup.n signal. ...
|
|
|
Design-for-testability method for path delay faults and test pattern generation method for path delay faults
OF THE INVENTION First Embodiment A first embodiment of the present invention relates to a design-for-testability method of changing the design of an integrated circuit ...
|
|
|
Method for optimizing test development for digital circuits
The present invention provides test patterns to detect timing related failures in large digital ICs, to rapidly detect least slack paths. Such digital ICs typically ...
|