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Switchable pull-ups and pull-downs for IDDQ testing of integrated circuits |
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Testing of digital-to-analog converters |
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Method and apparatus for failure detection utilizing functional test vectors and scan mode |
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Testing apparatus embedded in scribe line and a method thereof |
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Method and apparatus for light-controlled circuit characterization |
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Method and system for instrumenting simulation models |
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Facilitating simulation of a model within a distributed environment |
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Method and system for fast maximum a posteriori decoding
| Details |
Inventors: Lerzer, Jurgen;
Assignee: Telefonaktiebolaget LM Ericsson (publ) (Stockholm, SE)
Primary Examiner: Chung; Phung M.
Assistant Examiner: Chase; Shelby A
Attorney, Agent or Firm: Burns, Doane, Swecker & Mathis, L.L.P.
Processing delay associated with MAP decoding (and variants thereof) is reduced by processing forward and reverse state metrics in parallel. Further reductions in processing complexity can be achieved by omitting redundant operations and multiplexing processing units' functionality. |
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DETAILED DESCRIPTION In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular circuits, circuit components, techniques, etc. in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known methods, devices, and circuits are omitted so as not to obscure the description of the present invention. To initialize this discussion it is appropriate to provide some additional details regarding the MAP decoding algorithm, as well as exemplary variants such as the Log-MAP algorithm and the Max-Log-MAP algorithm to provide some context in which to consider the present invention. In the following discussion certain variables are used, as defined below. S. sub. k is the state for the k-th node in the trellis. The metric calculations involve probabilities whose notation is given as follows. Let A, B and C be events, then the following definitions are valid: P(A): probability of the event A P(A, B): probability of the joint events A and B P(A, B, C): probability of the joint events A, B and C P(A. vertline. B): conditional probability of the event A given the occurrence of the event B P(A, B. vertline. C): conditional probability of the joint events A and B given the occurrence of the event C P(A. vertline. B, C): conditional probability of the event A given the occurrence of the joint events B and C The MAP Algorithm The MAP Algorithm includes the following four steps: 1. Branch Transition Metric Calculation (BTMC): Calculation of the Branch Transition Metrics . gamma. . sub. k (S. sub. k-1,S. sub. k) from the symbols y. sub. k received over the channel 12: . gamma. . sub. k (S. sub. k-1,S. sub. k)=P(y. sub. k,S. sub. k. vertline. S. sub. k-1)=P(y. sub. k. vertline. S. sub. k-1,S. sub. k). multidot. P(S. sub. k. vertline. S. sub. k-1) (1) 2. Forward State Metric Calculation (FSMC): Recursive calculation of the Forward State Metrics
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