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Method and system for measuring signal propagation delays using ring oscillators
| Details |
Inventors: Patrie, Robert D.; Wells, Robert W.; Young, Steven P.; Kingsley, Christopher H.; Chung, Daniel; Conn, Robert O.;
Assignee: Xilinx, Inc. (San Jose, CA)
Primary Examiner: Miska; Vit
Assistant Examiner:
Attorney, Agent or Firm: Behiel; Arthur J., Young; Edel M.
A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with an inverting feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the test circuit. One embodiment of the invention includes a phase discriminator that samples the output of the oscillator and accumulates data representing the duty cycle of that signal. The duty cycle can then be combined with the average period of the test signal to determine, separately, the delays associated with falling and rising edges propagating through the test circuit. |
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DETAILED DESCRIPTION FIG.
2 is a schematic diagram of a conventional tester 200 connected to an FPGA 210 that has been configured to implement an oscillator and to determine the period and the high and low duty cycles of the oscillator.
The purpose of the depicted configuration is to determine the propagation delay for signals traversing test circuit 215 from an input node 220 through an output node 225 and back to input node 220.
Test circuit 215 might be any signal path for which the signal propagation delay is of interest.
Test circuit 215 is configured to form a path through elements of FPGA 210 for which delay is to be measured.
The invention allows a user to separately measure the propagation delays associated with the rising and falling edges of logic signals.
Input node 220 of test circuit 215 is connected to a test counter 230 via a buffer 232, and is driven by the output terminal of an AND gate 235.
Output node 225 of test circuit 215 is connected back to input node 220 via an inverting input terminal of AND gate 235.
The remaining input terminals of AND gate 235 are connected to a test-enable line TE and a global test-enable line GTE, both from tester 200.
Test counter 230 is a conventional counter connected via a test-count line (or lines) TCNT to tester 200.
A reset line (not shown) connected between tester 200 and test counter 230 allows tester 200 to reset test counter 230 to zero.
Global test-enable line GTE conveys a global test-enable signal to any number of test circuits on FPGA 210; test-enable TE is specific to test circuit 215.
The use of two test-enable lines allows a number of different test circuits to share test circuitry.
For example, the test clock signals TCLK from a number of test circuits can be logically ORed and the result input to test counter 230.
Counter 230 would then only accumulate data for the active one of the test circuits.
Similarly, the HC/LC signals from a number of test circuits can be logically ORed and the result input to HENTR 265.
The phase discrimators 240 and 245 would be duplicated, one for each test circuit 215
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