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Home Fault Detection Method-and-system-for-storing-device-test-information-on-a-semiconductor-device-using-on-device-logic-for-determination-of-test-results

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Details
Inventors: McBride, Jerry D.;
Assignee: Micron Technology, Inc. (Boise, ID)
Primary Examiner: Ton; David
Assistant Examiner: Chase; Shelly A
Attorney, Agent or Firm: TraskBritt

A method and system for testing a semiconductor device and storing device test results in nonvolatile memory elements on the tested device, in which the semiconductor device includes logic circuitry which allows test results to be determined on the device. Test results are stored temporarily in one or more latch elements on the semiconductor device and are subsequently stored in nonvolatile memory elements. The invention eliminates the need for device testing equipment to perform a determination of test results and thus may simplify the design of test equipment. In one embodiment of the invention, passing test results are stored in a mixed code of set and unset nonvolatile memory elements such that the test results contain information about correct application of test signals as well as correct functioning of the semiconductor device.

DETAILED DESCRIPTION OF THE INVENTION A schematic diagram of an embodiment of the present invention is shown in FIG.
1.
An integrated circuit device is indicated at 1, and the integrated circuit device tester used for testing the integrated circuit device is indicated at 2.
Integrated Circuit Device Tester Integrated circuit device tester 2 may be used for testing integrated circuit device 1.
Integrated circuit device tester 2 is configured for sending a test signal on test signal line 21 and a test address signal on test address line 22.
The test address signal specifies the address on integrated circuit device 1 to which the test signal is to be sent.
Integrated circuit device tester 2 is also configured for sending a set signal on set signal line 23 and a set address signal on set address line 24.
Lines 21, 22, 23 and 24 may be single lines or may be buses that carry multiple signals or bits of data.
The set address signal indicates the address of the nonvolatile memory element which is to be set to indicate whether the device has passed or failed a particular test or test step.
Integrated circuit device tester 2 has the capability of being programmed to perform multiple test steps, at each test step delivering a particular test signal to a particular address or set of addresses and subsequently sending a set signal and set address signal to select the nonvolatile memory device address memory which is to store the results of the test step.
The set signal does not cause the nonvolatile memory element to be set directly, but enables setting of the nonvolatile memory element by circuitry on integrated circuit device 1.
Integrated circuit device tester 2 performs similarly to testers currently used in integrated circuit device testing.
However, integrated circuit device tester 2 does not need to perform many of the functions conventionally performed by prior testers.
For example, without limitation, integrated circuit device tester 2 does not need to perform the functions of reading values from integrated circuit device 1, comparing these values with expected values and, based on the results of the comparison, generating an instruction for setting a fuse or other nonvolatile memory element on integrated circuit device 1



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