Method for data width conversion between a DMA controller and an interface unit with a bus width that is an integer multiple of the DMAC bus width

DETAILED DESCRIPTION Accordingly, it is the primary objective of this invention to provide a method and system which perform simple data transfer between a direct memory access controller and an interface unit while permitting the system to be more compact.
One embodiment of the invention pertains to a data transfer method using a direct memory access controller having a plurality of first bus lines having a first bus width and an interface unit having a plurality of second bus lines having a second bus width which is greater than the first bus width.
The method includes the steps of: (1) connecting sub bus lines of the second bus lines (the sub bus lines corresponding in number to the first bus lines) to the first bus lines, (2) connecting a predetermined voltage to other bus lines in the second bus lines, excluding the sub bus lines connected to the first bus lines, via a resistor element; and (3) transferring data between the direct memory access controller and the interface unit using the first bus lines and the sub bus lines.
In the method of one embodiment, the second bus lines may respectively correspond to data from upper bit data to lower bit data, and the sub bus lines may correspond to data consisting of a plurality of bits including a least significant bit.
The second bus width may be set to an integer multiple of the first bus width.
Furthermore, the data transfer step may include a step of transferring data the number of bytes of which is an integer multiple of the number of data bytes transferable by the direct memory access controller.
In another embodiment of the invention, a data transfer system includes a direct memory access controller having a plurality of first bus lines which have a first bus width, and an interface unit having a plurality of second bus lines which have a second bus width greater than the first bus width.
The sub bus lines of the second bus lines, which correspond in number to the first bus lines, are connected to the first bus lines.
The system also includes a resistor element connected between a predetermined voltage and other bus lines in the second bus lines excluding the sub bus lines connected to the first bus lines