Method for optimizing test development for digital circuits

DETAILED DESCRIPTION The present invention provides test patterns to detect timing related failures in large digital ICs, to rapidly detect least slack paths.
Such digital ICs typically include a plurality of gates, such that each gate has at least one input pin and at least one output pin.
An output pin of a first gate is coupled to the input pin of a second gate through a wire.
The present invention reduces the number of tests on the IC by determining the slowest path through the pins on the gates.
This path is used to test the slowest path through each pin on every gate in the circuit.
A delay value through each gate in the circuit is calculated, as well as a value for branch depth and a value for branch width.
The invention determines a least slack path based on the delay, branch depth, and branch width.
Further calculations are performed for reconvergent fanout and detection of fortuitous faults along one or more fanout-free regions.
The invention identifies a path (the least slack path) upon which a timing related error at a fault site is more likely to be triggered by a pattern intended to detect the fault site.
The present invention also extends the functionality of a transition fault model by determining a delay value associated with a detected transition fault and thereby provides a qualitative measure of delay test coverage.
A list of fault sites tested is produced, providing information as to the total degree of coverage.
The development of such test patterns according to the present invention provides qualitative and quantitative information for faults tested, and avoids exponential runtimes for path generation.
The present invention develops such test patterns using existing software and hardware, and can reveal small delay defects that might go undetected using prior art testing techniques.
Such testing reliably extracts the longest delay path through every pin on every gate in a device using two static traverses of a levelized gate netlist.
Other features and advantages of the invention will appear from the following description in which the preferred embodiments have been set forth in detail, in conjunction with the accompanying drawings