Home | Links | Contact Us | More About Intellectual Property | Bookmark
Search patents:
Home Fault Detection Method-for-predicting-a-fill-up-level-of-a-buffer-in-an-ATM-network-element

 Multiple BIST controllers for testing multiple embedded memory arrays
The present invention generally relates to various models representing at least a portion of a ...


 Boundary scan latch configuration for generalized scan designs
The present invention relates generally to a boundary design of a chip. More particularly, the ...


 RAM memory circuit having a plurality of banks and an auxiliary device for testing
One aspect of the invention is directed to designing a RAM memory circuit provided with a plurality ...


 Apparatus for testing an interconnecting logic fabric
According to the present invention, test circuitry and operational methods that are formed within ...


 Radio channel control apparatus used in a CDMA cellular system and capable of changing cell size
It is therefore an object of this invention to provide a radio channel control apparatus capable of ...


 Multiple satellite repeater management system using frame error rate for diversity selection
The foregoing and other problems are overcome and the objects of the invention are realized by ...


 Adaptive power control in wideband CDMA cellular systems (WCDMA) and methods of operation
I claim: 1. A Wide-band Code Division Multiple Access ("WCDMA") system comprising: a base station ...


 Link-quality estimation method and components for multi-user wireless communication systems
OF THE PREFERRED EMBODIMENT(S) The present invention is directed to wireless communication systems ...


 Transmission power control method and transmission power control apparatus in mobile communication system
1. A transmission power control method characterized in that: reception quality of a signal ...


 Drilling restart control system
It is therefore an object of the present invention to provide a drilling restart control system of ...


 Method for predicting a fill-up level of a buffer in an ATM network element

Details
Inventors: Saari, Jarmo;
Assignee: Nokia Corporation (Espoo, FI)
Primary Examiner: Ngo; Ricky Q.
Assistant Examiner: Wong; Warner
Attorney, Agent or Firm: Cohen, Pontani, Lieberman & Pavane

The present invention proposes a method for predicting a fill-up level of a buffer in an ATM network element, wherein for a respective one of at least one ongoing transmission connection (T1, . . . Ti, . . . Tn) via said ATM network element (ATM_NWE), cells (C1, . . . , Ci, . . . , Cn) are input to said buffer (BUF) with a respective input cell rate, and said ATM network element outputs said cells at a predetermined output cell rate; comprising the steps of: measuring a momentary fill-up level of said buffer after each respective time interval (A), determining a slope of the fill-up level of said buffer for the immediately preceding time interval, and estimating the fill-up level of said buffer to be reached after the subsequent time interval based on said slope of the fill-up level for the immediately preceding time interval. Also, the present invention proposes a method for connection admission control for such an ATM network element said method making use of the proposed scheme for predicting a fill-up level of said buffer in said ATM network element, and further denies and/or accepts a new transmission connection requested to be handled by said ATM network element based on the predicted fill-up level of said buffer. Still further, the present invention aims at correspondingly adapted control devices within an ATM network.

DETAILED DESCRIPTION Hence, it is an object of the present invention to provide an improved method for predicting a fill-up level of a buffer in an ATM network element, and also to provide an improved method for connection admission control for an ATM network element comprising a buffer.
Also, the present invention aims at the provision of a corresponding control device in an ATM network.
According to the present invention, the above first object is achieved by a method for predicting a fill-up level of a buffer in an ATM network element, wherein for a respective one of at least one ongoing transmission connection via said ATM network element, cells are input to said buffer with a respective input cell rate, and said ATM network element outputs said cells at a predetermined output cell rate; the method comprising the steps of: measuring a momentary fill-up level of said buffer after each respective time interval, determining a slope of the fill-up level of said buffer for the immediately preceding time interval, and estimating the fill-up level of said buffer to be reached after the subsequent time interval based on said slope of the fill-up level for the immediately preceding time interval.
Furthermore, according to the present invention, the above second object is achieved by a method for connection admission control for an ATM network element comprising a buffer, wherein for a respective one of at least one ongoing transmission connection via said ATM network element, cells are input to said buffer with a respective input cell rate, and said ATM network element outputs said cells at a predetermined output cell rate; said method comprising the steps of: predicting a fill-up level of said buffer in said ATM network element according to any modification of the above mentioned method, and denying and/or accepting a new transmission connection requested to be handled by said ATM network element based on the predicted fill-up level of said buffer.
Still further, the present invention proposes an accordingly adapted control device in an ATM network



Related patents
  DSL modem utilizing low density parity check codes
It is therefore an object of the invention to provide simple methods of generating reproducible H matrices. It is another object of the invention to provide DSL modems ...
  Structured document management system, structured document management method, search device and search method
The present invention has been made in view of the above circumstances and provides a structured document management system and a structured document management method ...
  High speed read/modify/write memory system and method
One form of the present invention is an improvement for a data processing system. The improvement comprises a memory for storing data elements, a first cache register ...
  Methods and apparatus for caching a location index in a data storage system
Aspects of the present invention relate to improved techniques for accessing content in a storage system. In accordance with one embodiment of the present invention, ...
  Method and apparatus for correcting data errors
Broadly speaking, the present invention relates to an error correcting method and apparatus which shortens the time needed to perform error correction using a buffer ...
  Method and apparatus for enhancing data rate in processing ECC product-coded data arrays in DVD storage subsystems and the like
What is claimed is: 1. A machine-implementable method for enhancing the data transfer rate in an arrangement formed by an ECC processor coupling a first memory, said ...
  Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method
OF THE INVENTION Hereinafter, referring to the accompanying drawings, embodiments of the present invention will be explained. In a structure of an error-correcting ...
  Method for testing integrated circuits having a grid-based, "cross-check" t e
The present invention is a new test structure which allows up to 100 percent electrical testing of Very Large Scale Integrated Circuits by the addition of an array of ...
  Serial scan chain architecture for a data processing system and method of operation
What is claimed is: 1. A data processor having a scan chain architecture, the scan chain architecture comprising: a plurality of scan chains wherein each scan chain in ...
  Hierarchically managed boundary-scan testable module and method
OF THE DRAWINGS FIG. 1 is a block diagram of electronic system 10 that accommodates JTAG testing through the use of a hierarchically managed testable module 12. System 1...

0.014

Archive: All patents - Links

Copyright (c)2006 Eipa-patents.org - All rights reserved