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Boundary scan latch configuration for generalized scan designs |
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RAM memory circuit having a plurality of banks and an auxiliary device for testing |
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Method for snooping raid 1 read transactions by a storage device
| Details |
Inventors: Young, B. Arlen;
Assignee: Adaptec, Inc. (Milpitas, CA)
Primary Examiner: Peugh; Brian R.
Assistant Examiner:
Attorney, Agent or Firm: Gunnison, McKay & Hodgson, L.L.P., Gunnison; Forrest
To implement a RAID 1 transaction, an initiator sends a single command, i.e., either a single read command, or a single write command, over a common I/O bus to a primary target device. A mirror target device snoops the common I/O bus and upon detecting the single command directed to the primary target device, effectively performs in the same manner as if the command had been directed to the mirror target device. Hence, a single command is used to effectuate a mirrored transaction. |
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DETAILED DESCRIPTION A target device snooping method, according to one embodiment of the present invention, minimizes the utilization problems of a host system and an initiator associated with prior art RAID 1 mirroring, while providing the same functionality and robustness. In one embodiment, an initiator and a pair of RAID 1 storage devices on are a common input/output(I/O) bus. One device in the pair of RAID 1 storages devices is designated a primary target device and the other device in the pair is designated a mirror target device. To implement a RAID 1 transaction, the initiator sends a single command, i. e. , either a single read command, or a single write command, over the common I/O bus to the primary target device. The mirror target device snoops the common I/O bus and upon detecting the single command to the primary target device, effectively performs in the same manner as if the command had been directed to the mirror target device. Hence, for a RAID 1 command, e. g. , a mirrored transaction, a single hardware I/O control block is generated by a host software driver that includes a mirror manager and an initiator manager, and is transferred over a host I/O bus to the initiator, which in one embodiment is a SCSI host adapter integrated circuit. The host system stores only a single hardware I/O control block for the mirrored transaction. Only one command block is generated by the mirror manager and delivered to the initiator manager for each RAID 1 transaction. This saves host CPU execution time and memory relative to the prior art RAID 1 methods that generated two command blocks for each mirrored transaction. Also, only one hardware I/O control block is generated by the initiator manager and delivered to the initiator. Hence, host bus bandwidth also is saved by not having to transfer two hardware I/O control blocks for each mirrored transaction. In addition, initiator sequencer execution time and initiator array memory space are saved by not having to generate a second hardware I/O control block for the mirrored transaction
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