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Details
Inventors: Gheewala, Tushar R.;
Assignee: Cross-Check Technology, Inc. (San Jose, CA)
Primary Examiner: Wieder; Kenneth A.
Assistant Examiner: Burns; William J.
Attorney, Agent or Firm: Townsend and Townsend

A new test structure is described which allows full testing of highly complex Integrated Circuits. The test structure consists of a grid of externally as well as individually accessible probe-lines and sense-lines with electronic switches at the crossings of said probe and the sense-lines. One end of the switches is tied to an array of test-points on the IC that are to be either monitored or controlled during the testing, and the other end of the switches is tied to a sense-line. The ON and the OFF states of the switches are controlled by probe-lines. The probe and sense lines are connected to test electronics, thus permitting the test electronics to control the electrical signals on the probe-lines and to measure or apply signals on the sense-lines. Thus, by the excitation of an appropriate probe-line and the monitoring of an appropriate sense-line, the test signals present at any one of the test-points can be measured. Conversely, by the excitation of an appropriate probe-line and application of a test signal on another appropriate sense-line the electrical signal on any of the test-points can be externally controlled for the purpose of testing.

DETAILED DESCRIPTION The present invention is a new test structure which allows up to 100 percent electrical testing of Very Large Scale Integrated Circuits by the addition of an array of test-points in the Integrated Circuit (IC).
According to the broadest aspects of the present invention, the test structure consists of a multi-dimensional array of externally accessible "probe-lines" and "sense-lines" with an electronic switch at each intersection of the probe-lines with the sense-lines.
The probe-lines and the sense-lines are electrically connected to external text electronics by the means of probe-points.
One end of each of the electronic switches is tied to a test-point on the IC where an electrical signal is to be either measured or controlled during test and the other end of the switch is tied to a said sense-line.
The ON and the OFF states of the electronic switches are controlled by probe-lines.
Thus, by applying signal levels on the probe-lines one at a time and by external monitoring of the signals present on the sense-lines, the electrical test signals at every intersections of the probe-lines and sense-lines can be measured.
For example, a 100.
times.
100, 2-dimensional, array consisting of 100 probe-lines and 100 sense-lines would allow direct testing of up to 10,000 test-points on the IC, however, requiring only 200 additional probe-points which must be connected to external test electronics through mechanical probes.
This number of external probe-points can however be further reduced by accessing the probe-lines and the sense-lines through dedicated on-chip test electronics consisting of serial/parallel shift-registers on the IC being tested.
Thus, further reducing the external probe-point requirement to less than 10 as compared to the 200 probe-point requirement mentioned above.
Besides being able to measure the absence or the presence of a signal at a test-point, this test structure also permits the measurement of analog parameters such as voltage amplitude and current sourcing and sinking capabilities of an electronic circuit



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