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Method of stress testing integrated circuit having memory and integrated circuit having stress tester for memory thereof
| Details |
Inventors: So, Jason Siucheong;
Assignee: STMicroelectronics, Inc. (Carrollton, TX)
Primary Examiner: Le; Vu A.
Assistant Examiner:
Attorney, Agent or Firm: Galanthay; Theodore E., Jorgenson; Lisa K., Regan; Christopher F.
An integrated circuit having enhanced testing capabilities and a method of testing an integrated circuit are provided. The integrated circuit preferably includes a substrate and a memory block on the substrate. The memory block preferably has a plurality of memory cells arranged in a plurality of rows and a plurality of columns within a defined area on the substrate, at least one bit line connected to each of the plurality of memory cells and defining a column, at least one word line connected to each of the plurality of memory cells and defining a row, and sense amplifying means connected to the at least one bit line for sensing a state of an addressed memory cell in at least one of the plurality of columns. The integrated circuit also includes a selectable stress tester on the substrate and connected to the memory block for selectively stress testing only portions of the memory block and not other portions so as to determine whether to accept or reject a memory block. |
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DETAILED DESCRIPTION With the foregoing in mind, the present invention advantageously provides a method of stress testing an integrated circuit having memory and an integrated circuit having stress tester for memory of the integrated circuit which significantly reduces the amount of time required to test the memory.
Also, the incremental density of the circuitry of an integrated circuit according to the present invention advantageously remains relatively unchanged.
The integrated circuit and method of the present invention, for example, advantageously reduces what can be a lengthy 2-3 month AC stress testing of memory, e.
g.
, RAM, on an integrated circuit to only a few days.
This reduction advantageously saves time and resources for the manufacturer.
The shortening of the AC qualification testing further allows manufacturers to ship product much more quickly to customers.
More particularly, the present invention provides an integrated circuit having enhanced testing capabilities.
The integrated circuit preferably has a substrate and a memory block on the substrate.
The memory block preferably includes a plurality of rows and a plurality of columns within a defined area on the substrate.
At least one bit line is connected to each of the plurality of memory cells and defines a column.
At least one word line also is connected to each of the plurality of memory cells and defines a row.
Sense amplifying means is connected to the at least one bit line for sensing a state of an addressed memory cell in at least one of the plurality of columns.
Selectable stress testing means is formed on the substrate and is connected to the memory block for selectively stress testing only selected portions of the memory block and not others so as to determine whether to accept or reject a memory block.
The present invention also includes methods of testing an integrated circuit having a block of memory formed thereon.
A method preferably includes generating a high frequency waveform signal and generating a test pattern across boundaries between only two columns and only two rows of the memory block, i
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Fault Detection 
