Methods and apparatus for resetting a monitored system using a gray code with alternating check bits

DETAILED DESCRIPTION This need is met by the invention of the present application wherein methods and apparatus are provided for monitoring systems which progress through a series of states or program steps, such as software controlled computers, by means of a watchdog timer which samples at least two check bits generated by a system being monitored with the check bits being generated such that only one can change its logic state between valid samples of the check bits.
The monitored system is reset if a fault within the system results in an error in the normal sequence through the series of states or program steps such that more than one of the check bits changes from sample to sample.
In addition, if the sequence becomes static such that no bits change within the check bits from sample to sample, a time-out will occur which also resets the monitored system.
In accordance with one aspect of the present invention, a timer for resetting a monitored system comprises output logic for generating a reset signal for the monitored system.
A counter having a clear input and an overflow output connected to the output logic counts pulses from a source of periodic pulses.
A monitored system error detector periodically samples at least two check bits from the monitored system which normally operates to generate the at least two check bits in a series of states with successive states differing from one another by only one bit.
The error detector generates a pass signal on a first output coupled to the clear input of the counter for each sample of the at least two check bits wherein only one of the at least two check bits changes state from the succeeding sample; and, generates an error signal on a second output connected to the output logic for each sample of the at least two check bits wherein more than of the at least two check bits has changed state from the succeeding sample.
The output logic generates a reset signal for the monitored system in response to an overflow of the counter or the error signal from the monitored system error detector