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Methods for maximizing routability in a programmable interconnect matrix having less than full connectability
| Details |
Inventors: Nazarian, Hagop A.; Douglass, Stephen M.; Graf, W. Alfred; Raza, S. Babar; Rajan, Sundar; Borzin, Shiva Sorooshian; Newman, Darren;
Assignee: Cypress Semiconductor Corp. (San Jose, CA)
Primary Examiner: Teska; Kevin J.
Assistant Examiner: Frejd; Russell W.
Attorney, Agent or Firm: Blakely, Sokoloff, Taylor Zafman LLP
Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w.sub.mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w.sub.mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors. According to a second embodiment, a predictive swapping technique is used whereby successfully routed signals qualified to provide a blocked signal with a route are first checked to determine whether a successful routing will be provided before swapping in the blocked output signal. |
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DETAILED DESCRIPTION The connectivity, connectability and routability of a connection circuit, hereinafter "programmable interconnect matrix" or "PIM," are, as stated above, characteristics of the PIM that are quite interrelated.
Because the connectivity of the PIM directly affects the amount of die space required for the PIM, the connectivity of the PIM is more likely to be the characteristic that drives the design of the PIM.
Regardless of the level of connectivity chosen by the designer, the connectability of the PIM should be optimized to provide maximum routability for the desired level of connectivity.
A purchaser of the PIM determines which input conductors of the PIM are connected to which output conductors of the PIM by programming the programmable elements of the PIM.
Because the manufacturer cannot predict every use of the PIM, providing maximum routability for a given level of connectivity better ensures that the purchaser of the PIM will be able to successfully program the PIM.
The discussion of PIMs that follows assumes that the pin assignment for the associated CPLD remains fixed.
In this manner, the routability of a PIM having a given level of connectability can be accurately assessed because, as described above, even a PIM that provides a maximum of one chance to route for each input signal is "fully routable" in the sense that the pin assignments of the CPLD can be altered to provide a route for any particular combination of input signals.
To reduce the die area required to implement a PIM, a basic assumption for any PIM design is that the connectivity of the PIM is such that the PIM is less than fully connectable.
Thus, not every input conductor of the PIM can be connected to every output conductor of the PIM.
Given this assumption, the first question is whether the PIM will also be less than fully routable.
If a fully routable PIM is desired, the minimum level of connectivity is constrained, as described below.
If full routability is not required, the level of connectivity is not constrained, but the PIM design should be optimized such that maximum routability and connectability are provided for the given level of connectivity
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Fault Detection 
