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| Method and apparatus for G.706 frame alignment and CRC procedure test tool |
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Microprocessor system generating instruction fetch addresses at high speed
| Details |
Inventors: Maeda, Toshinori; Kawada, Tomoharu; Miyake, Jiro;
Assignee: Matsushita Electric Industrial Co., Ltd. (Osaka, JP)
Primary Examiner: Bowler; Alyssa H.
Assistant Examiner: Donaghue; L.
Attorney, Agent or Firm: Lowe, Price, LeBlanc & Becker
A microprocessor system which comprises an arithmetic logic unit for generating flags, a flag update detector for outputting a flag update detecting signal, a status register coupled to the flag update detector and the arithmetic logic unit for receiving the flag update detecting signal and a flag outputted from the arithmetic logic unit, a first address outputting portion coupled to the flag update detector and the status register for receiving the flag update detecting signal, a flag outputted from the status register, a target instruction address, a next instruction address and a branch condition for determining according to the flag received from the status register whether or not the branch condition is met, and for outputting first and second address candidates selected from the target instruction address and the next instruction address according to the flag update signal and to whether or not the branch condition is met, and a second address outputting portion coupled to the first address outputting portion and the arithmetic logic unit for receiving the first and second address candidates outputted from the first address outputting portion, the branch condition and the flag outputted from the arithmetic logic unit, for determining according to the flag received from the arithmetic logic unit whether or not the branch condition is met, and for outputting the target instruction address or the next instruction address as an instruction fetch address on the basis of a result of determining according to the flag received from the arithmetic logic unit whether or not the branch condition is met. |
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DETAILED DESCRIPTION To achieve the foregoing object and in accordance with the present invention, there is provided a microprocessor system which comprises an arithmetic logic unit for generating flags, a flag update detector for outputting a flag update detecting signal, a status register coupled to the flag update detector and the arithmetic logic unit for receiving the flag update detecting signal and a flag outputting from the arithmetic logic unit, a first address outputting portion coupled to the flag update detector and the status register for receiving the flag update detecting signal, a flag outputted from the status register, a target instruction address, a next instruction address and a branch condition of a conditional branch instruction, for determining according to the flag received from the status register whether or not the branch condition is met, and for outputting first and second address candidates selected from the target instruction address and the next instruction address according to the flag update signal and to whether or not the branch condition is met, and a second address outputting portion coupled to the first address outputting portion and the arithmetic logic unit for receiving the first and second address candidates outputted from the first address outputting portion, the branch condition of the conditional branch instruction and the flag outputted from the arithmetic logic unit, for determining according to the flag received from the arithmetic logic unit whether or not the branch condition is met, and for outputting the target instruction address or the next instruction address as an instruction fetch address on the basis of a result of determining according to the flag received from the arithmetic logic unit whether or not the branch condition is met.
Thereby, can be omitted the flag selecting circuit which selects the flag outputted from the status register and the flag outputted from the ALU in accordance with the flag update detecting signal.
Thus, the flag outputted from the ALU can be directly inputted to the second address outputting portion
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