Models and technique for automated fault isolation of open defects in logic

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS The present invention comprises a technique that includes diagnostic fault models and an associated algorithm to automate the diagnosis of open defects (a.
k.
a.
, open fault)--that is defects that cause interconnects to be open or have high resistance in logic.
Two diagnostic fault models, the node and net models, are used to predict potential logic errors that could be caused at the outputs of a logic circuit in the presence of an open fault on any interconnect under consideration in the circuit.
Typically, the output of the logic circuit could either be the bond pads of a chip or observable points within an integrated circuit, such as scan nodes, scanout nodes or memory arrays that are directly accessible during testing.
The predicted errors are compared with actual errors observed during testing of the circuit using a diagnostic matching algorithm that ranks the presence of open defects on all interconnects under consideration in the circuit.
The problem of determining the logic behavior of an open interconnect is a difficult one, as illustrated by the simple logic circuit shown in FIG.
1A.
The logic circuit includes AND gates 10, 12, and 14, which are electrically by interconnect lines 16, 18, 20, and 22.
Ideally, signals at the outputs and inputs of the AND gates would pass through appropriate interconnect lines with no disturbance.
However, under an open fault condition, a signal may not pass through properly (i.
e.
, not pass through at all, or pass through at a different logic level than the signal was when it left the previous gate.
The logic value of the signal under an open fault is a function of the location of the defect, its resistance, and the capacitive coupling of the signal line to power and ground signals lines and other neighboring signal lines at logic 1 (V.
sub.
DD) or logic 0 (GND).
For example, the behavior of an open fault at locations 24, 26, 28, and 32 along the interconnect circuitry, as depicted in the Figure, may be different