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| Optical network and switch control method for use in the optical network |
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| System for transmitting optical data |
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Monitor TEG test circuit
| Details |
Inventors: Ukei, Toshio; Aoyagi, Hiroshi;
Assignee: Kabushiki Kaisha Toshiba (Kawasaki, JP)
Primary Examiner: Karlsen; Ernest
Assistant Examiner:
Attorney, Agent or Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Monitor TEGs (Test Element Groups) for extracting the effects of process variations within a semiconductor chip and a test circuit therefor are provided to allow the monitor TEGs to be tested after package sealing. A plurality of monitor TEGs and a control circuit for selectively enabling the monitor TEGs are formed on the same chip as a semiconductor device is formed. The monitor TEGs are placed in selected positions in the chip and selectively monitored via test signals, thereby implementing process parameter monitoring by means of the device parameter variations within the finished chip. The external terminals of the semiconductor device are configured such that they are programmed via enable signals to serve as input/output terminals of the test signals, keeping the number of the external terminals of the semiconductor device from increasing for the testing purpose. |
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DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views, and more particularly to FIGS.
1-4 thereof, there are illustrated various exemplary embodiments of the present invention.
FIG.
1 shows a test circuit for monitor TEGs formed in a semiconductor chip according to a first embodiment of the present invention.
The monitor TEG test circuit shown in FIG.
1 comprises a plurality of monitor TEGs 1 to 5 formed at the four corners of and on the inside of a semiconductor chip 10, each TEG consisting of a ring oscillator, a TEG control circuit 6 for selectively controlling the monitor TEGs, a five-input NOR gate 7 connected at its inputs to receive output signals A.
sub.
1 to A.
sub.
5 of the respective monitor TEGs 1 to 5 and having its output connected to an external terminal 12, and an external terminal 11 for inputting a test signal T.
sub.
0 to the TEG control circuit.
The TEG control circuit 6 is connected to receive test signals T.
sub.
1 to T.
sub.
5 as well as the test signal T.
sub.
0 and to output control signals G.
sub.
1 to G.
sub.
5 to the monitor TEGs 1 to 5.
With the external terminals 11 and 12 are respectively associated enable gates 8 and 9 which permit output data DATA.
sub.
1 and DATA.
sub.
2 of a semiconductor device formed on the same chip to be output to outside.
FIG.
2 shows an arrangement of the TEG control circuit 6, which comprises five two-input NAND gates 61 to 65 each of which is connected at its two inputs to receive the test signal T.
sub.
0 and a respective one of the test signals T.
sub.
1 to T.
sub.
5 to provide a corresponding one of the control signals G.
sub.
1 to G.
sub.
5 for the monitor TEGs 1 to 5.
Hereinafter, the circuit operation when process parameters are monitored will be described by way of an example of testing the monitor TEG 2.
At this time, the enable gates 8 and 9 are respectively disabled by enable signals E.
sub.
1 and E.
sub.
2 from connecting the output data DATA
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