 Optimizing repeaters positioning along interconnects |
| A preferred embodiment of the present invention provides an aspect of interconnect design for ... |
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| Method and apparatus for placing repeaters in a network of an integrated circuit |
| OF THE PREFERRED EMBODIMENT(S) FIG. 1 is a schematic diagram of a network or net 100 that is used ... |
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| Parasitic element extraction apparatus |
| It is an object of the present invention to solve at least the problems in the conventional ... |
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| Bist architecture for measurement of integrated circuit delays |
| The IC to be tested is provided with, in one embodiment, a two-wire test bus, which passes near ... |
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| Oscillator for measuring on-chip delays |
| FIG. 2 is a schematic diagram of an oscillator 200 configured, in accordance with the invention, ... |
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| Method and system for measuring signal propagation delays using ring oscillators |
| FIG. 2 is a schematic diagram of a conventional tester 200 connected to an FPGA 210 that has been ... |
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| Monitor TEG test circuit |
| OF THE PREFERRED EMBODIMENTS Referring now to the drawings, wherein like reference numerals ... |
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| IC substrate noise modeling including extracted capacitance for improved accuracy |
| An invention is described herein which provides methods and apparatus for modeling noise present in ... |
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Monolithically integrated semiconductor circuit
| Details |
Inventors: Michael, Ewald;
Assignee: Siemens Aktiengesellschaft (Berlin and Munich, DE)
Primary Examiner:
Assistant Examiner:
Attorney, Agent or Firm:
A monolithically integrated digital semiconductor circuit includes an address decoder, inputs connected to the address decoder for supplying external addressing signals thereto, a test decoder connected to the address decoder and connected to the external addressing signal supply inputs for directly receiving at least part of the external addressing signals, circuit parts to be addressed being connected to and controlled by the test decoder, a switch-over section connected to the test decoder for supplying a specific switch-over signal thereto causing the test decoder to be activated and causing the address decoder to be placed in a rest condition. |
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DETAILED DESCRIPTION I claim: 1.
Monolithically integrated digital semiconductor circuit, comprising an address decoder, first means connected to said address decoder for supplying external addressing signals thereto, a test decoder connected to said address decoder and connected to said external addressing signal supply means for directly receiving at least part of said external addressing signals, second means being connected to and controlled by said test decoder, a switching circuit being responsive to a specific switchover signal, operatively connected to the address decoder and to said test decoder for causing said test decoder to be activated and causing said address decoder to be placed in a rest condition.
2.
Semiconductor circuit according to claim 1, in combination with a test circuit monolithically combined with the semiconductor circuit, wherein said second means are part of said test circuit.
3.
Semiconductor circuit according to claim 1, including an external terminal for feeding in said switch-over signal.
4.
Semiconductor circuit according to claim 1, comprising signal inputs being connected to said switching circuit for supplying a specific combination of digital input signals causing said switching circuit to generate said switch-over signal.
5.
Semiconductor circuit according to claim 1, including a supply voltage source, said test decoder and address decoder being formed of identical circuits, and said switching circuit being in the form of third means for disconnecting said address decoder from said supply voltage source when said switching circuit is activated and for simultaneously connecting said test decoder to said supply voltage source.
6.
Semiconductor circuit according to claim 1, wherein said address decoder is automatically deactivated when said test decoder is activated.
7.
Semiconductor circuit according to claim 1, wherein said test decoder and address decoder include self-blocking MOS field-effect transistors.
8.
Semiconductor circuit according to claim 7, wherein said transistors are of the same channel type
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Fault Detection 
