Home | Links | Contact Us | More About Intellectual Property | Bookmark
Search patents:
Home Fault Detection Monolithically-integrated-semiconductor-store

 Method and system for measuring signal propagation delays using ring oscillators
FIG. 2 is a schematic diagram of a conventional tester 200 connected to an FPGA 210 that has been ...


 Monitor TEG test circuit
OF THE PREFERRED EMBODIMENTS Referring now to the drawings, wherein like reference numerals ...


 System, IC chip, on-chip test structure, and corresponding method for modeling one or more target interconnect capacitances
In summary, the present invention comprises a system, an IC chip, a test structure formed on the IC ...


 IC substrate noise modeling including extracted capacitance for improved accuracy
An invention is described herein which provides methods and apparatus for modeling noise present in ...


 Method for performing coupling analysis
Deterministic evaluation of coupling noise voltage is a function of many physical and electrical ...


 Cell-based noise characterization and evaluation
OF THE INVENTION Aspects of the present invention include methods and apparatus for designing an ...


 Adaptive test program generation
It is an advantage of some aspects of the present invention that an event handling mechanism is ...


 Hybrid interface for packet data switching
The invention allows parallel transfer of data without the limitation imposed by the phase ...


 System and method for approximating the coupling voltage noise on a node
OF THE PREFERRED EMBODIMENT Having summarized various aspects of the present invention, reference ...


 Method and system for testing interconnected integrated circuits
The problems identified above are addressed by a system, device, and method for dynamically testing ...


 Monolithically integrated semiconductor store

Details
Inventors: Meusburger, Gunther;
Assignee: Siemens Aktiengesellschaft (Berlin & Munich, DE)
Primary Examiner: Fears; Terrell W.
Assistant Examiner:
Attorney, Agent or Firm: Hill, Van Santen, Steadman, Chiara & Simpson

A monolithically integrated semiconductor store is disclosed having a plurality of storage elements on a semiconductor layer with each storage element having a storage capacitor and a selector element. The selector element includes first and second transfer gates. The first transfer gate connects to a word decoder and the second transfer gate similarly connects to a word decoder at a different input. The source-drain path of the first transfer gate connects to the storage capacitor and the source-drain path of the second transfer gate connects to an evaluator and regenerator circuit via a bit line. With the integrated store disclosed, for a given number of storage elements, the bit lines are reduced to approximately half their length and the number of requisite word lines is reduced by half as compared to previous integrated stores.

DETAILED DESCRIPTION An object of the invention is to further reduce the storage space required for a semiconductor store of the noted type.
This is achieved in accordance with the invention by providing each storage element with a storage capacitor connected in series with first and second transfer gates.
The first transfer gate has its gate connected to a word line and the second transfer gate has its gate connected to another line connecting with the word decoder.
The source-drain paths of the first and second transfer gates are connected in series to a bit line.
The bit lines are provided as doped zones of opposite conductivity type which are provided at a surface of a semiconductor layer.
First and second strips of a first conductive coating are applied on an insulating layer over the semiconductor layer on each side of the bit lines.
A further insulating layer is provided over the first and second strips.
A second conductive coating is applied over the second insulating layer such that it lies over the first and second strips and also extends between a gap between the first and second strips.
The word line connects with the second conductive coating.
The advantage which can be attained by the invention is that in a storage field comprising a given number of storage elements, in comparison to conventional forms of storage the number of requisite word lines is reduced by half, and the bit lines are reduced to approximately half their length.
This provides the possibility of substantially reducing the capacitance of the storage capacitors while maintaining the reliability of analysis of the stored information, which leads to a significant reduction in the semiconductor area required for the individual storage element and thus for the entire store.



Related patents
  Configurable digital wireless and wired communications system architecture for implementing baseband functionality
The present invention comprises a configurable multiprocessor communications architecture which performs various digital communications functions and which is ...
  Adaptive digital radio communication system
An illustrative embodiment of the adaptive digital radio communications system according to the principles of the present invention is described below. Here we disclose ...
  Programmable, reconfigurable DSP implementation of a Reed-Solomon encoder/decoder
This invention relates to programmable, reconfigurable implementations of Reed-Solomon encoder/decoder devices that could be cast into one of three separate designs. The ...
  Method and apparatus for transcoding coded picture signals from object-based coding to block-based coding
The invention provides a transcoder for transcoding a coded object-based picture signal that represents a picture to a coded block-based picture signal that also ...
  Optimizing repeaters positioning along interconnects
A preferred embodiment of the present invention provides an aspect of interconnect design for optimizing delay characteristics of interconnects. The preferred embodiment ...
  Method and apparatus for placing repeaters in a network of an integrated circuit
OF THE PREFERRED EMBODIMENT(S) FIG. 1 is a schematic diagram of a network or net 100 that is used to illustrate repeater insertion in accordance with the present ...
  Parasitic element extraction apparatus
It is an object of the present invention to solve at least the problems in the conventional technology. The parasitic element extraction apparatus extracts parasitic ...
  Voltage controlled oscillator including voltage controlled delay circuit with power supply noise isolation
Accordingly, one object of the present invention is a VCO which is less sensitive than prior art VCOs to power supply noise. Another object of the present invention is a ...
  Bist architecture for measurement of integrated circuit delays
The IC to be tested is provided with, in one embodiment, a two-wire test bus, which passes near each circuit node of interest. Each node which is an input to a delay ...
  Oscillator for measuring on-chip delays
FIG. 2 is a schematic diagram of an oscillator 200 configured, in accordance with the invention, to include a pair of similar test circuits 210A and 210B. Test circuits ...

0.014

Archive: All patents - Links

Copyright (c)2006 Eipa-patents.org - All rights reserved