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| Methods and apparatus for caching a location index in a data storage system |
| Aspects of the present invention relate to improved techniques for accessing content in a storage ... |
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| Method and apparatus for correcting data errors |
| Broadly speaking, the present invention relates to an error correcting method and apparatus which ... |
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| Method for testing integrated circuits having a grid-based, "cross-check" t e |
| The present invention is a new test structure which allows up to 100 percent electrical testing of V... |
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| Serial scan chain architecture for a data processing system and method of operation |
| What is claimed is: 1. A data processor having a scan chain architecture, the scan chain ... |
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| Hierarchically managed boundary-scan testable module and method |
| OF THE DRAWINGS FIG. 1 is a block diagram of electronic system 10 that accommodates JTAG testing ... |
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| Multiple BIST controllers for testing multiple embedded memory arrays |
| The present invention generally relates to various models representing at least a portion of a ... |
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Multi-threading for a processor utilizing a replay queue
| Details |
Inventors: Merchant, Amit A.; Boggs, Darrell D.; Sager, David J.;
Assignee: Intel Corporation (Santa Clara, CA)
Primary Examiner: Donaghue; Larry D.
Assistant Examiner:
Attorney, Agent or Firm: Antonelli, Terry, Stout & Kraus, LLP
A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store long latency instruction for each thread until the long latency instruction is ready to be executed (e.g., data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled. |
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DETAILED DESCRIPTION I.
Introduction According to an embodiment of the present invention, a processor is provided that speculatively schedules instructions for execution and includes a replay system.
Speculative scheduling allows the scheduling latency for instructions to be reduced.
The replay system replays instructions that were not correctly executed when they were originally dispatched to an execution unit.
For example, a memory load instruction may not execute properly if there is a L0 cache miss during execution, thereby requiring the instruction to be replayed (or re-executed).
However, one challenging aspect of such a replay system is the possibility for long latency instructions to circulate through the replay system and re-execute many times before executing properly.
One example of a long latency instruction could be a memory load instruction in which there is a L0 cache miss and a L1 cache miss (i.
e.
, on-chip cache miss) on the first execution attempt.
As a result, the execution unit may then retrieve the data from an external memory device across an external bus which can be very time consuming (e.
g.
, requiring several hundred clock cycles).
The unnecessary and repeated re-execution of this long latency load instruction before its source data has returned wastes valuable execution resources, prevents other instructions from executing and increases application latency.
Where there are multiple threads, one thread can stall due to a long latency instruction, thereby inhibiting execution of the other threads.
Therefore, according to an embodiment, a replay queue is provided for temporarily storing the long latency instruction and its dependent instructions.
When the long latency instruction is ready for execution (e.
g.
, when the source data for a memory load instruction returns from external memory), the long latency instruction and the dependent instructions can then be unloaded from the replay queue for execution.
According to an embodiment, the processor may include multiple replay queues, with at least one replay queue being provided per thread or program flow (for example)
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Fault Detection 
