 Replacement data error detector |
| A cache is described which includes an error circuit for detecting errors in the replacement data. I... |
|
| Soft error detection in high speed microprocessors |
| The present invention provides aspects for soft error detection for a superscalar microprocessor. T... |
|
| Semiconductor integrated circuit device, manufacturing method thereof, and driving method for the same |
| To solve the above-described problems, the present invention employs the below-mentioned means. As ... |
|
| Integration of security modules on an integrated circuit |
| In accordance with the preferred embodiment of the present invention, an integrated circuit ... |
|
| Semiconductor memory with a multiplexer for selecting an output for a redundant memory access |
| The invention may be incorporated into an integrated circuit memory with redundant memory cells, by ... |
|
| Method and apparatus for inhibiting a predecoder when selecting a redundant row line |
| One aspect of the invention comprises a circuit for replacing a defective signal path of a ... |
|
| Random access memory having a flexible array redundancy scheme |
| The present invention is a wide I/O Random Access Memory (RAM) and the architecture and redundancy ... |
|
| Integrated circuit chip with a wide I/O memory array and redundant data lines |
| The present invention is an integrated circuit chip with a RAM or a RAM macro with at least one ... |
|
| Improved logic cell array using CMOS E.sup.2 PROM cells |
| OF ILLUSTRATIVE EMBODIMENT Referring now to the drawings, FIG. 1 is a schematic block diagram of a ... |
|
|
Multiple BIST controllers for testing multiple embedded memory arrays
| Details |
Inventors: Crouch, Alfred Larry; McKeown, Jennifer Lynn; Shepard, Clark Gilson;
Assignee: Motorola, Inc. (Schaumburg, IL)
Primary Examiner: Teska; Kevin J
Assistant Examiner: Knox; Lonnie A.
Attorney, Agent or Firm: Hayden; Bruce, Toler; Jeffrey G.
Multiple memory arrays (215, 225) in embedded applications are each tightly coupled to their own Built-In Self-Test (BIST) controller to form BISTed memory cells (210, 220) supporting structural and retention testing. Testing on multiple BISTed memories (210, 220) is initiated by common INVOKE (230), RETENTION (240), and RELEASE (250) signals. DONE and HOLD signals are combined (260, 280) from the multiple BISTed memories (210, 220) and delayed to generate a global "all memory" DONE (265) and HOLD (285) signals. FAIL signals are combined (270) from the multiple BISTed memories (210, 220) to generate a global "any memory" FAIL (275) signal. The BISTed memories can be combined in multiple stages to meet power limitations. |
|
DETAILED DESCRIPTION The present invention generally relates to various models representing at least a portion of a semiconductor device and various semiconductor devices.
In accordance with a particular embodiment, the model includes a plurality of memory arrays; and a plurality of test circuit controllers, wherein test data is concurrently read from at least one element within each of the plurality of memory arrays during a retention test controlled by the plurality of test circuit controllers.
In accordance with another embodiment, the model includes a plurality of memory arrays; and a plurality of test circuit controllers, wherein test data is concurrently read from at least one element within each of the plurality of memory arrays during a test controlled by the plurality of test circuit controllers, a first memory array of the plurality of memory arrays associated with a first of the plurality of test circuit controllers to control testing of the first memory array and a second memory array of the plurality of memory arrays associated with a second of the plurality of test circuit controllers to control testing of the second memory array independently of the first memory array.
In accordance with a further embodiment, the semiconductor device includes a plurality of memory arrays; and a plurality of test circuit controllers configured to test the plurality of memory arrays, wherein test data is retrieved from the plurality of memory arrays concurrently during a retention test in response to at least one phase of a test sequence controlled by the plurality of test circuit controllers.
In accordance with another embodiment, the semiconductor device includes a plurality of memory arrays; and a plurality of test circuit controllers configured to test the plurality of memory arrays, wherein test data is retrieved form the plurality of memory arrays concurrently in response to at least one phase of a test sequence controlled by the plurality of test circuit controllers.
A first memory array of the plurality of memory arrays is associated with a first of the plurality of test circuit controllers to control testing of the first memory array, and a second memory array of the plurality of memory arrays is associated with a second of the plurality of test circuit controllers to control testing of the second memory array independently of the first memory array
|
|
Fault Detection 
