Multiple bit error detection and correction system employing a modified Reed-Solomon code incorporating address parity and catastrophic failure detection

DETAILED DESCRIPTION Accordingly, it is a primary objective of the present invention to provide an error correction and detection technique for semiconductor memory arrays which processes a data word from memory, in parallel, through combinatorial logic using a modified Reed-Solomon code which can detect and correct multiple-bit failures.
This modified Reed-Solomon code has been adapted to also detect incorrect memory accesses (addressing) and catastrophic failures in the data word.
Generally, the present invention comprises a semiconductor memory array coupled by a bus arrangement to an error correction and detection logic device.
Data words are stored in the memory array at separate locations identified by an address.
In addition, check bits are stored in memory at the corresponding address where the appropriate data word is stored.
The present invention utilizes a modified Reed-Solomon code with a "symbol" size of four bits.
A symbol represents a unit of bits for which the Reed-Solomon code detects and corrects errors.
The data word consists of 32 data bits (eight symbols).
Twelve check bits (three check symbols) including at least one address parity bit are appended to every data word, making the total word length 44 bits (eleven symbols).
The code can correct one, two, three or four bits in error, as long as they are confined to a single symbol (single symbol error correction) and it can detect two through eight bits in error as long as they are confined to two symbols (double symbol error detection).
Before a data word is stored into memory, both the data word and the address of the location in memory where the data word is to be stored are passed through the error detection and correction logic device.
This logic device performs calculations to generate the appropriate check bits for the data word and its corresponding address.
The data word and check bits are then stored in the memory array.
When a data word is read from memory, a similar process occurs.
The data word, its check bits, and the address generated to read the data word and check bits from memory, are passed through the error detection and correction logic device