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| Virtual multi-port RAM |
| It is therefore an object of the present invention to provide a multi-port RAM structure which ... |
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| Decoding global drive/boot signals using local predecoders |
| One aspect of the invention comprises a decoding circuit for driving a word line associated with at ... |
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| Semiconductor memory device having even and odd numbered bank memories |
| An object of this ivention is to provide a semiconductor memory device which can simultaneously ... |
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| Semiconductor memory device having split operation and capable of reducing power supply noise |
| An object of the present invention is to provide a semiconductor memory device that effectively ... |
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| Monolithically integrated semiconductor circuit |
| I claim: 1. Monolithically integrated digital semiconductor circuit, comprising an address decoder, ... |
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| Semiconductor device with component circuits under symmetric influence of undesirable turbulence |
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| Memory output circuit |
| I claim: 1. In a semiconductor memory, an output circuit comprising: an output transistor series ... |
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| High voltage switching circuit in a nonvolatile memory |
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Multiple bit output dynamic random-access memory
| Details |
Inventors: Reese, Edmund A.; Spaderna, Dieter W.; Flannagan, Stephen T.;
Assignee: Intel Corporation (Santa Clara, CA)
Primary Examiner: Popek; Joseph A.
Assistant Examiner:
Attorney, Agent or Firm: Blakely, Sokoloff, Taylor & Zafman
A dynamic MOS random-access memory is described which includes a circuit for permitting checking of the on chip refresh counter. The memory also includes a refresh generator, the frequency of which automatically varies to compensate for temperature variations. Other innovations include an arbitration circuit, a hidden refresh function and unique accessing of redundant lines. |
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DETAILED DESCRIPTION An improvement for a dynamic random-access memory which includes memory cells coupled to sense amplifiers by bit lines is described.
The memory includes a digital counter for selecting cells in the array for refreshing; one improvement of the present invention is a means for checking this counter.
For this improvement the memory includes writing means for writing binary zeros into predetermined cells and charging means for charging the bit lines interconnecting these cells with the sense amplifiers.
Disabling means coupled to the sense amplifiers prevent the sensing (by the amplifiers) of the binary data stored in the cells.
Rather, as the cells are accessed by the counter, charge from the bit lines changes the data stored in the cells from binary zeros to binary ones.
Then, through reading means, the cells are read to verify that they all contain binary ones.
If they do, it can be assumed that the counter is working properly and that all the cells have been accessed.
On the other hand, if some of the cells still contain binary zeros, it can be assumed that the counter (or other circuitry) has failed.
Other unique aspects of the described memory include a refresh generator, the frequency of which automatically changes with the memory temperature.
More refreshing occurs at higher temperatures to compensate for the higher leakage in the capacitive storage cells.
Since the signals from the refresh generator are asychronous with memory access signals, simultaneous occurrence of these signals is possible, causing a "lock-up".
The memory includes a unique arbitration circuit for preventing this condition.
Also, the refreshing of the memory cells, when possible is performed so as to hide the refresh cycle from the user.
This "smart" refreshing substantially reduced the handling of "ready" signals, or like signals, between the memory, and for example, a microcomputer.
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Fault Detection 
