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Multiprocessor computer backlane bus
| Details |
Inventors: Myers, Mark; Lloyd, Stacey; Stout, Richard; Takasumi, Robert; Lynch, John;
Assignee: Pyramid Technology Corporation (San Jose, CA)
Primary Examiner: Chung; Phung M.
Assistant Examiner:
Attorney, Agent or Firm: Burns, Doane, Swecker & Mathis, LLP
A computer bus includes a first original signal line, a second redundant signal line, circuitry connected to the first original signal line and the second redundant signal line for driving the first original signal line and the second redundant signal line so as to convey on each identical information, circuitry for receiving signals on the first original signal line and the second redundant signal line, and error checking circuitry for comparing the signals on the first original signal line and the second redundant signal line and for indicating an error if the signals differ. By providing redundant signals for each signal that cannot be check with parity (for example wired-OR signals), the potential for single undetected points of failure is eliminated. In accordance with another embodiment of the invention, a computer having multiple modules connected by a backplane bus. |
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DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following detailed description describes the logical, electrical, and connector specifications of Pyramid Technology Corporation's R-B us.
The R-Bus is a proprietary backplane bus used to connect boards in Pyramid Technology NILE series systems.
The R-Bus is a high-performance, block-oriented system bus that supports multiprocessor cache coherency, extensive error checking, and hardware fault tolerance.
Referring to FIG.
1, in a preferred embodiment, the R-Bus allows up to 30 boards to be connected to a R-Bus.
Each board is identified by its slot, from slot 1 to slot 30.
Some slots may be empty and some slots may contain boards.
A board may contain up to four modules, designated module 0 to module 3.
A particular R-Bus implementation may support fewer boards.
For example, a smaller system's R-Bus implementation might support 12 slots.
Processor boards, memory boards, I/O boards, and other board types may be intermixed on the R-Bus.
In other implementations, clock boards, certain I/O boards, or boot processor boards may be restricted to certain slots.
Electrically, in an exemplary embodiment, the R-Bus is a synchronous bus with a clock rate of 25 MHz.
The R-Bus uses BTL (Bus Transceiver Logic) transceivers for most signals.
The R-Bus data transfer path is 128 bits wide.
The bus bandwidth is 400 Mbytes per second peak, 267 Mbytes per second for writes, 228 Mbytes per second for reads.
Logically, the R-Bus provides block transfer operations (64 bytes) and "partial" operations used to read or write 1, 4, or 8 bytes at a time.
Read operations are split into separate read request and read response transactions, allowing other bus traffic to use the R-Bus during the actual memory access.
A typical R-Bus block transfer consists of one address/command bus cycle followed by several data cycles followed by one rest cycle.
Each data cycle transfers 16 bytes.
For example, a block write consists of one address/command cycle followed by four data cycles, followed by one rest cycle, a total of six cycles
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Fault Detection 
