 Redundant address decoder |
| Accordingly, an object of the present invention is to provide a redundant address decoder which can ... |
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| Automatic transition charge pump for nonvolatile memories |
| Generally, the present invention provides a high voltage charge pump for programming a non-voltage ... |
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| High speed static BiCMOS memory with dual read ports |
| A memory includes a plurality of cells with each cell containing a pair of cross-coupled N-channel ... |
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| Flexible redundancy architecture and fuse download scheme |
| What is claimed is: 1. In an integrated circuit comprising a plurality of circuit elements, some of ... |
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| Flexibilitiy for column redundancy in a divided array architecture |
| The present invention relates to an apparatus and method for implementing flexible redundancy ... |
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| Row redundancy block architecture |
| It is therefore an object of the present invention to provide a redundancy block architecture which ... |
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| Shortened timeout period during frame retry in a communication link |
| The present invention is embodied in a system and method for asynchronously transmitting data ... |
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| Media access control receiver and network management system |
| Broadly speaking, the present invention fills these needs by providing methods and apparatuses for ... |
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Multiprocessor programmable interrupt controller system adapted to functional redundancy checking processor systems
| Details |
Inventors: Sarangdhar, Nitin V.; Papworth, Dave; Nizar, P. K.; Carson, David G.;
Assignee: Intel Corporation (Santa Clara, CA)
Primary Examiner: Ray; Gopal C.
Assistant Examiner:
Attorney, Agent or Firm: Blakely, Sokoloff, Taylor & Zafman
A multiprocessor programmable interrupt controller system, for use in a multiprocessor system in which one processor unit is a functional redundant checking (FRC) unit, has a synchronous interrupt bus, distinct from the system (memory) bus, with an interrupt bus clock that has a frequency that is a subharmonic of the FRC unit master CPU clock, for handling interrupt request (IRQ) related messages and maintaining synchronism between the master and checker CPUs of the FRC unit. Additional embodiments provide for the use of D-type flip-flop synchronizers to accommodate FRC units whose internal (core) clock or external bus clock are not harmonically related to the interrupt clock frequency. Each processor unit has an interrupt acceptance unit (IAU) coupled to the interrupt bus for the acceptance of IRQs and for broadcasting of IRQs generated by its associated on-chip processor. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs) that are each coupled to the interrupt bus for broadcasting of I/O-generated IRQs. The interrupt bus is a synchronous three-wire bus having one clock wire and two data wires for 2-bit parallel-serial data transmission. Arbitration for control of the interrupt bus by the IAUs and IDUs uses one of the data wires. Lowest priority IRQ delivery mode uses a similar one-wire arbitration procedure for determining which IAU has the lowest current priority task running in its associated on-chip processor. A modification to the lowest priority mode arbitration procedure also provides for uniform distribution of IRQs to eligible processors. The actual servicing of the IRQs is done by means of the system bus. |
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DETAILED DESCRIPTION It is the object of the current invention to provide a multiprocessor programmable interrupt controller (MPIC) system including, but not limited to, the following capabilities: 1) a means for properly synchronizing interrupt requests to FRC units; 2) a separate Interrupt Bus, distinct from the memory (or system) bus, for communication of interrupt request (IRQ) and IRQ receipt acknowledgment signals, and for IRQ service arbitration between eligible servers; 3) interrupt servicing of multiple I/O peripheral subsystems, each with its own set of interrupt lines; 4) static as well as dynamic multiprocessor interrupt management; 5) programmable interrupt vector and steering information for each IRQ pin; 6) interprocessor interrupts allowing any processor to interrupt any other for dynamic reallocation of interrupt tasks; 7) operating system defined programmable reallocation of interrupt tasks; and 8) support of system-wide functions related to nonmaskable interrupt (NMIs), processor reset, and system debugging.
The present invention achieves these capabilities by means of a MPIC system structure that includes three major subsystem components: 1) an Interrupt Bus, separate and distinct from the memory (system) bus; 2) an I/O Interrupt Delivery Unit (IDU) connected to the Interrupt Bus and to a set of IRQ pins, having a Redirection Table for processor selection and interrupt priority and vector information; and 3) a processor associated Interrupt Acceptance Unit (IAU) connected to the Interrupt Bus for managing interrupt requests for a specific system processor including acceptance acknowledgment, IRQ pending, nesting and masking operations, and interprocessor interrupt management.
More specifically, the present invention uses a three-wire synchronous bus, two wires for data, one wire for the clock, and one of the two data wires for bus and lowest priority arbitration.
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Fault Detection 
