Non-volatile RAM cell with enhanced conduction insulators

DETAILED DESCRIPTION What is claimed is: 1.
A memory system comprising; a semiconductor substrate, a volatile memory cell having a data node formed in said substrate, a non-volatile device including: a floating gate capacitively coupled to said substrate, a first control gate, a thin insulating layer disposed between said floating gate and said first control gate, a second control gate, and a dual charge injector structure disposed between said floating gate and said second control gate, means for coupling one of said control gates of said non-volatile device to said data node, and means for applying control pulses to the other of said control gates of said non-volatile device for selectively transferring data between said data node and said floating gate.
2.
A memory system as set forth in claim 1 wherein said dual charge injector structure is a dual electron injector structure.
3.
A memory system as set forth in claim 1 wherein said charge injector structure has a capacitance substantially smaller than the capacitance formed by said first control gate, said insulating layer and said floating gate.
4.
A memory system as set forth in claim 3 wherein said charge injector structure is an electron injector structure having at least one layer of silicon-rich silicon dioxide.
5.
A memory system as set forth in claim 4 wherein said electron injector structure is a dual electron injector structure having two layers of silicon-rich silicon dioxide separated by a layer of substantially impurity-free silicon dioxide.
6.
A memory system as set forth in claim 1 wherein said memory cell includes an input/output transistor and said floating gate is disposed between said input/output transistor and said data node.
7.
A memory system as set forth in claim 1 wherein said memory cell includes a voltage source terminal and said floating gate is disposed between said terminal and said data node.
8.
A memory system as set forth in claim 7 wherein said memory cell includes a load resistor disposed between said terminal and said floating gate