Optical disk apparatus having error correction circuit

DETAILED DESCRIPTION OF THE INVENTION There will now be described an embodiment of this invention with reference to the accompanying drawings.
FIG.
1 shows an optical disk apparatus of this invention.
A disk motor 101 drives and rotates an optical disk 102.
A laser pickup 103 used as an optical head, for example, reads a sync.
code and data, both recorded in the each of the sectors of the optical disk, by applying a beam to a pit string on the optical disk 102.
The pickup 103 thereby detects the reflected beam by use of a built-in photodiode (not shown) or the like and converts the detected beam into an RF signal.
An RF amplifier 104 amplifies an RF signal output from the laser pickup 103 and subjects the amplified RF signal to the waveform equalization process.
Further, the RF amplifier 104 creates and outputs a focus error signal 105 and tracking error signal 106.
A servo control circuit 107 compensates for the gains and phases of the focus error signal 105 and tracking error signal 106 output from the RF amplifier 104 to drive an actuator (not shown) in the laser pickup 103.
Thus, the stable focus servo and tracking servo can be effected.
A slicer 108 binary-codes an RF signal output from the RF amplifier 104 into a 1-bit digital signal.
A data PLL circuit 109 reproduces a bit clock signal 110 in synchronism with the RF signal supplied from the slicer 108.
A serial/parallel conversion circuit 111 serial/parallel-converts the 1-bit RF signal supplied from the slicer 108 in the unit of 16 bits.
As described before, the S/P conversion timing signal is created based on the sync.
code in the DVD signal.
A sync.
code detection circuit 112 detects a sync.
code (SY0 to SY7) shown in FIG.
4B from the binary-coded RF signal supplied from the slicer 108.
A frame counter 113 counts (32+1456) bits in one frame in synchronism with the sync.
code supplied from the sync.
code detection circuit 112.
A timing signal generating circuit 114 generates a timing signal for the S/P conversion circuit 111 or the like based on the count of the frame counter 113