Optimizing repeaters positioning along interconnects

DETAILED DESCRIPTION A preferred embodiment of the present invention provides an aspect of interconnect design for optimizing delay characteristics of interconnects.
The preferred embodiment further provides a method for analyzing the delay characteristics of interconnects for verifying interconnect design results.
Interconnect delay characteristics are improved by inserting repeaters at predetermined intervals along interconnects in a metal layer.
The metal layer is any one of a plurality of metal layers in a semiconductor device that embodies an integrated circuit (IC).
Typically, each interconnect in the metal layer has at least one neighboring interconnect.
The position of repeaters along every other interconnect in the metal layer is shifted relative to the position of repeaters along their neighboring interconnect(s).
To achieve improved interconnect delay characteristics, the positioning of repeaters along interconnects is optimized by adjusting the position shift based on factors such as repeaters physical characteristics and signal waveforms.
In accordance with the purpose of the invention, as embodied and broadly described herein, the invention relates to a method for optimizing repeaters positioning along interconnects.
Specifically, the method includes inserting repeaters in positions along a first interconnect at predetermined intervals that are related to signal transition times.
The method further includes inserting repeaters in positions along a second interconnect at the predetermined intervals, the second interconnect being a neighbor of the first interconnect.
The positions along the second interconnect are offset, by a predetermined length, relative to the positions along the first interconnect so that the repeaters along the second interconnect are shifted relative to the repeaters along the first interconnect.
The predetermined length is half (0.
5) of the predetermined intervals such that repeaters are phase shifted by half, wherein the interconnect delay that corresponds to the offsetting by half of the predetermined interval minimizes the interconnect delay under worst case conditions