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Oscillator for measuring on-chip delays
| Details |
Inventors: Alfke, Peter H.;
Assignee: Xilinx, Inc. (San Jose, CA)
Primary Examiner: Miska; Vit
Assistant Examiner:
Attorney, Agent or Firm: Behiel, Esq.; Arthur J., Young; Edel M.
A circuit separately measures one or both of the rising-edge and falling-edge signal propagation delays through a signal path of interest. The greater of these delays can then be used to establish a worst-case delay for the signal path. The worst-case delay can be used, in turn, to create accurate timing specifications for logic circuits that include similar or identical signal paths. To determine the delay through the signal path, the signal path is used with a second, typically identical, signal path to create alternating feedback paths of an oscillator. The oscillator is configured to output a test-clock signal having a period proportional to either the rising- or falling-edge delays through the two signal paths. The test-signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the signal path of interest. |
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DETAILED DESCRIPTION FIG.
2 is a schematic diagram of an oscillator 200 configured, in accordance with the invention, to include a pair of similar test circuits 210A and 210B.
Test circuits 210A and 210B might be any signal paths for which the associated signal propagation delays are of interest.
In one embodiment, for example, test circuits 210A and 210B are signal paths on a field-programmable gate array (FPGA).
Oscillator 200 provides a test-clock signal TCLK on a like-named output terminal.
The period T.
sub.
TCLK of test-clock signal TCLK is a function of the propagation delay for rising-edge signals traversing test circuits 210A and 210B.
The period T.
sub.
TCLK can therefore be used to determine the rising-edge delays D.
sub.
RA and D.
sub.
RB for respective test circuits 210A and 210B.
Other embodiments of the invention can be used to measure falling-edge delays, and yet other embodiments allow a user (e.
g.
, a test engineer) to separately measure the propagation delays associated with the rising and falling edges of logic signals.
Test circuits 210A and 210B are included within a pair of respective signal paths 215A and 215B.
Signal path 215A includes an output terminal 220 connected to the "0" input of a multiplexer 225; signal path 215B includes an output terminal 230 connected to the "1" input of multiplexer 225.
Output terminal TCLK connects to respective input terminals of signal paths 215A and 215B and to the select input S of multiplexer 225.
Also included in signal paths 215A and 215B are a respective pair of inverters 235A and 235B.
Inverter 235A is connected between output terminal TCLK and an input terminal 240 of test circuit 210A.
Inverter 220B is connected between an output terminal 245 of test circuit 210B and the "1" input of multiplexer 225.
In the present example, test circuits 210A and 210B are assumed to be non-inverting, though the invention is not so limited.
FIG.
3 is a simple waveform diagram 300 depicting the operation of oscillator 200 of FIG.
2.
Each waveform in FIG
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