Parasitic element extraction apparatus

DETAILED DESCRIPTION It is an object of the present invention to solve at least the problems in the conventional technology.
The parasitic element extraction apparatus extracts parasitic elements based on logical netlist information that defines cell information for defining cells of a semiconductor integrated circuit and nets showing connection between the cells, layout information that defines position information on wiring patterns of the cells and the nets connecting the cells, the position information being used when placement and routing are carried out using the logical netlist information, and a library that defines capacitances and inductances for the wiring patterns.
The parasitic element extraction apparatus according to the present invention comprises a category classification unit that classifies the nets defined in the logical netlist information based on a constraint that defines at least two categories of a first category to a third category among five categories; and a parasitic element extraction unit that extracts the parasitic elements while attention is paid to any one of the capacitances and the inductances defined in the constraint for each of the classified nets, and generates connection information including the extracted parasitic elements.
The five categories are a first category related to the nets adjacent a net of interest among the nets defined in the logical netlist information and having potentials of the adjacent nets being likely to change in a same direction as a direction of the potential of the net of interest; a second category related to the nets adjacent the net of interest and having the potentials likely to change in an opposite direction to the direction of the potential of the net of interest; a third category related to the nets adjacent the net of interest and having the potentials likely to change in both the same direction and the opposite direction to the direction of the potential of the net of interest; a fourth category related to the nets having the potentials fixed even when logical of the semiconductor integrated circuit changes; and a fifth category related to the nets adjacent the net of interest that do not affect any one of the capacitance and the inductance for the net of interest or that can ignore any one of the capacitance and the inductance for the net of interest