Partitioned dynamic memory allowing substitution of a redundant circuit in any partition and using partial address disablement and disablement override

DETAILED DESCRIPTION It is therefore an object of the present invention to provide a circuit architecture applicable, for example, to a DRAM memory and which is partitioned for parallel, concurrent refresh of all partitions and which also includes redundant circuits which may be freely allocated to any partition of the circuit.
It is another object of the invention to provide a flexible redundancy system which is compatible with partitioning of systems such as DRAM's for purposes such as parallel refresh and which covers multiple partitions.
It is a further object of the invention to provide a redundancy system for large memories with minimal redundant circuitry and addressing overhead.
It is yet another object of the invention to provide a redundant circuit system which precludes the driving of defective or marginally operative elements which have been replaced.
It is another further object of the invention to provide for simultaneous refreshing of multiple partitions of a memory within a single redundant circuit system.
In order to accomplish these and other objects of the invention, a method of operating a refreshable electronic device which has been divided into a plurality of addressable circuit systems and including a plurality of redundant circuits is provided including the steps of detecting a partial address corresponding to a circuit within an addressable circuit system for which a redundant circuit has been substituted, disabling energization of the partial address detected in said detecting step in all addressable circuit systems of said electronic device, and overriding said disabling step at said partial address in all other addressable circuit systems of said plurality of addressable circuit systems of said electronic device.
In accordance with another aspect of the invention, an electronic circuit is provided including a plurality of systems of addressable elements, a plurality of redundant circuits which can be substituted for portions of any of the systems of addressable elements, and an arrangement for driving at least one addressable element at a partial address in at least one of the plurality of systems of addressable elements simultaneously with at least one redundant circuit which has been substituted for at least one addressable element at the same partial address in another system of addressable elements