Personal computer memory bank parity error indicator

DETAILED DESCRIPTION Referring now to the drawing, a personal computer includes a microprocessor 10 connected to a main memory comprised of two memory banks 12 and 14 through two parity check units 16 and 18.
A memory control 20 is connected to the microprocessor and to the memory banks for controlling operation of the main memory.
The parity check units work in conventional fashion and are operative to generate parity error signals when parity errors are detected thereby.
During each main memory access, data is simultaneously read from or written into both banks 16 and 18.
If there is a parity error in the data being accessed for bank 12, parity check unit 16 will produce a first parity error signal.
If there is a parity error in the data being accessed for bank 14, parity check unit 18 will produce a second parity error signal.
Two latches or flip flops 22 and 24 have output lines 28 and 30 connected to the inputs of a two input OR circuit or logic unit 26.
The output lines are also respectively connected back to the clear inputs of the latches to latch up the output signals, when they arise.
Latches 22 and 24 further have input lines 25 and 27 respectively connected to outputs from parity check units 16 and 18.
The latches further have input lines 29 and 31 connected to memory control 20 to receive a clock signal from the address strobe line thereof.
When either parity check unit detects a parity error, during a memory access, a parity error signal is sent over its respective output line 25 or 27 to the appropriate one of latches 22 and 24 and upon receiving the next clock signal, such latch is set and produces an active output signal.
The active output from the set latch then switches OR circuit 26 to send a parity error signal to an interrupt controller 34.
This controller is connected by line 36 to an interrupt input of microprocessor 10 to initiate an interrupt in response to receiving a parity error signal from unit 26.
Output 30 from latch 22 is also connected to an input of a single bit position 41 of a register 40 of an addressable I/O port 38