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Programmable variable length high speed digital delay line
What is claimed is: 1. A variable length, high speed, digital delay line apparatus comprising in combination: a set of serially arranged, fixed-length, digital delay ...
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Bus station abort detection
An abort detection circuit for inclusion in each operational component of a multi-component system in which these components are interconnected through a bus that is ...
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Asynchronous anticontention logic for bi-directional signals
The present invention concerns an asynchronous anticontention circuit for a bi-directional bus. The asynchronous anticontention circuit comprises an anticontention ...
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Method of handshaking in a data communications bus
OF THE DRAWINGS Throughout this description, the preferred embodiment and examples shown should be considered as exemplars, rather than limitations on the apparatus and ...
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Apparatus for recognition of approximate shape of an article
What is claimed is: 1. A method for the recognition of the approximate shape of an article, which comprises finding from the projection of said article the largest width,...
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Clock generating circuit for use in single chip microcomputer
Accordingly, it is an object of the present invention to provide a basic clock signal generating circuit which has overcome the above mentioned defect of the ...
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Method and apparatus for power management of an integrated circuit
Embodiments of the present invention include a clock distribution system and clock interrupt system for an integrated circuit device. Ignoring effects associated with ...
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Adaptive expansion bus
The following sets forth a detailed description of the best contemplated mode for carrying out the invention. The description is intended to be illustrative of the ...
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Apparatus and method for synchronously providing a fullness indication of a dual ported buffer situated between two asynchronous buses
OF THE PREFERRED EMBODIMENT Referring to FIG. 1, there is illustrated a computer system C utilizing the preferred embodiment of the present invention. A central ...
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Apparatus and method of layering cache and architectural specific functions to permit generic interface definition
It is therefore one object of the present invention to provide an improved cache controller for a data processing system. It is another object of the present invention ...
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