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Preamplification-method-and-apparatus-for-dram-sense-amplifiers

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Preamplification method and apparatus for dram sense amplifiers

Details

Inventors: Furutani, Kiyohiro; Arimoto, Kazutami;
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP)
Primary Examiner: Fears; Terrell W.
Assistant Examiner:
Attorney, Agent or Firm: Lowe, Price, LeBlanc, Becker & Shur

A preamplifier is provided between a sense amplifier and a memory cell array at each bit line pair lead from a memory cell array. The preamplifier amplifies a potential difference between bit lines at the time of reading information from the memory cell and outputs the same to the sense amplifier. More specifically, the preamplifier charges a step-up capacitor and a step-down capacitor connected in parallel between the bit lines, and then connects these step-up capacitor and step-down capacitor to one input terminal of the sense amplifier in a positive direction and to the other input terminal in a negative direction, respectively. As a result, a potential of the one bit line is boosted and a potential of the other bit line is dropped.

DETAILED DESCRIPTION An object of the present invention is to improve reliability of read out in DRAM.
Another object of the present invention is to increase the potential difference applied to a sense amplifier of a DRAM for more reliable data read out therefrom.
A further object of the present invention is to increase the potential difference applied to a sense amplifier of a DRAM to provide more reliable read out of data therefrom without increasing cell storage capacitance.
A still further object of the present invention is to increase the potential difference applied to a sense amplifier of a DRAM to provide more reliable read out of data therefrom, without requiring reduce of bit line stray capacitance thereof.
A still further object of the present invention is to provide a DRAM having an improved bit line voltage preamplifier, wherein bit line voltage applied to the sense amplifier is amplified symmetrically.
A still further object of the present invention is to provide in a DRAM sense amplification that is high in speed and low in reading errors.
Briefly stated, the present invention includes a preamplifier as well as a sense amplifier provided between first and second bit lines of each bit line pair lead from a memory cell array.
Each preamplifier serves to amplify a potential difference produced between the two bit lines at the time of applying a reading signal to a memory and to output it to the corresponding sense amplifier.
Each preamplifier comprises a step-up capacitor for raising a potential of the first bit line, a step-down capacitor for lowering a potential of the second bit line, first switching means for connecting the respective step-up and step-down capacitors between the first bit line and the second bit line, and second switching means for connecting the step-up capacitor to one input terminal of the sense amplifier in series in a positive direction and also for connecting the step-down capacitor to the other input terminal of the sense amplifier in series in a negative direction

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